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base repository: m-labs/misoc
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head repository: m-labs/misoc
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compare: 6776e2275c64
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Jul 1, 2012

  1. framebuffer: register output of FIFO

    Sebastien Bourdeauducq committed Jul 1, 2012
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    8ba3118 View commit details
  2. Work around imbecilic timing constraints system

    Sebastien Bourdeauducq committed Jul 1, 2012
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    6776e22 View commit details
Showing with 9 additions and 2 deletions.
  1. +5 −0 constraints.py
  2. +4 −2 milkymist/framebuffer/__init__.py
5 changes: 5 additions & 0 deletions constraints.py
Original file line number Diff line number Diff line change
@@ -100,6 +100,11 @@ def get_ucf(self, ns):
TIMESPEC "TSphy_tx_clk" = PERIOD "GRPphy_tx_clk" 40 ns HIGH 50%;
TIMESPEC "TSphy_tx_clk_io" = FROM "GRPphy_tx_clk" TO "PADS" 10 ns;
TIMESPEC "TSphy_rx_clk_io" = FROM "PADS" TO "GRPphy_rx_clk" 10 ns;
NET "asfifo*/counter_read/gray_count*" TIG;
NET "asfifo*/counter_write/gray_count*" TIG;
NET "asfifo*/preset_empty*" TIG;
""".format(phy_rx_clk=ns.get_name(self._phy_rx_clk), phy_tx_clk=ns.get_name(self._phy_tx_clk))

return r
6 changes: 4 additions & 2 deletions milkymist/framebuffer/__init__.py
Original file line number Diff line number Diff line change
@@ -191,7 +191,6 @@ def get_fragment(self):
clkport="clk_write")
t = self.token("dac")
return Fragment([
Cat(self.vga_hsync_n, self.vga_vsync_n, self.vga_r, self.vga_g, self.vga_b).eq(asfifo.outs["data_out"]),
asfifo.ins["read_en"].eq(1),

self.endpoints["dac"].ack.eq(~asfifo.outs["full"]),
@@ -200,7 +199,10 @@ def get_fragment(self):

self.busy.eq(0),
asfifo.ins["rst"].eq(0)
], instances=[asfifo])
], [
Cat(self.vga_hsync_n, self.vga_vsync_n, self.vga_r, self.vga_g, self.vga_b).eq(asfifo.outs["data_out"])
],
instances=[asfifo])

class Framebuffer:
def __init__(self, address, asmiport):