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base repository: m-labs/misoc
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head repository: m-labs/misoc
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compare: bdb47e7977fb
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  • 2 commits
  • 3 files changed
  • 1 contributor

Commits on Feb 13, 2014

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    88d4962 View commit details
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    bdb47e7 View commit details
Showing with 13 additions and 19 deletions.
  1. +8 −8 misoclib/dvisampler/analysis.py
  2. +3 −9 misoclib/dvisampler/dma.py
  3. +2 −2 targets/mlabs_video.py
16 changes: 8 additions & 8 deletions misoclib/dvisampler/analysis.py
Original file line number Diff line number Diff line change
@@ -116,7 +116,7 @@ def __init__(self, word_width):
self.b = Signal(8)

# in sys clock domain
word_layout = [("parity", 1), ("pixels", word_width)]
word_layout = [("sof", 1), ("pixels", word_width)]
self.frame = Source(word_layout)
self.busy = Signal()

@@ -159,11 +159,12 @@ def __init__(self, word_width):
fifo.din.pixels.eq(cur_word),
fifo.we.eq(cur_word_valid)
]
new_frame_r = Signal()
self.sync.pix += [
If(new_frame_r, fifo.din.parity.eq(~fifo.din.parity)),
new_frame_r.eq(new_frame)
]
self.sync.pix += \
If(new_frame,
fifo.din.sof.eq(1)
).Elif(cur_word_valid,
fifo.din.sof.eq(0)
)
self.comb += [
self.frame.stb.eq(fifo.readable),
self.frame.payload.eq(fifo.dout),
@@ -196,10 +197,9 @@ def __init__(self, word_width):
self._r_overflow.w.eq(sys_overflow & ~overflow_mask),
self.overflow_reset.i.eq(self._r_overflow.re)
]
self.sync += [
self.sync += \
If(self._r_overflow.re,
overflow_mask.eq(1)
).Elif(self.overflow_reset_ack.o,
overflow_mask.eq(0)
)
]
12 changes: 3 additions & 9 deletions misoclib/dvisampler/dma.py
Original file line number Diff line number Diff line change
@@ -64,19 +64,13 @@ def __init__(self, lasmim, nslots):
alignment_bits = bits_for(bus_dw//8) - 1

fifo_word_width = 24*bus_dw//32
self.frame = Sink([("parity", 1), ("pixels", fifo_word_width)])
self.frame = Sink([("sof", 1), ("pixels", fifo_word_width)])
self._r_frame_size = CSRStorage(bus_aw + alignment_bits, alignment_bits=alignment_bits)
self.submodules._slot_array = _SlotArray(nslots, bus_aw, alignment_bits)
self.ev = self._slot_array.ev

###

# start of frame detection
sof = Signal()
parity_r = Signal()
self.sync += If(self.frame.stb & self.frame.ack, parity_r.eq(self.frame.payload.parity))
self.comb += sof.eq(parity_r ^ self.frame.payload.parity)

# address generator + maximum memory word count to prevent DMA buffer overrun
reset_words = Signal()
count_word = Signal()
@@ -122,8 +116,8 @@ def __init__(self, lasmim, nslots):

fsm.act("WAIT_SOF",
reset_words.eq(1),
self.frame.ack.eq(~self._slot_array.address_valid | ~sof),
If(self._slot_array.address_valid & sof & self.frame.stb, NextState("TRANSFER_PIXELS"))
self.frame.ack.eq(~self._slot_array.address_valid | ~self.frame.payload.sof),
If(self._slot_array.address_valid & self.frame.payload.sof & self.frame.stb, NextState("TRANSFER_PIXELS"))
)
fsm.act("TRANSFER_PIXELS",
self.frame.ack.eq(self._bus_accessor.address_data.ack),
4 changes: 2 additions & 2 deletions targets/mlabs_video.py
Original file line number Diff line number Diff line change
@@ -137,8 +137,8 @@ def __init__(self, platform, with_memtest=False):
self.submodules.fb = framebuffer.MixFramebuffer(pads_vga, pads_dvi,
self.lasmixbar.get_master(), self.lasmixbar.get_master())
_add_vga_tig(platform, self.fb)
self.submodules.dvisampler0 = dvisampler.DVISampler(platform.request("dvi_in", 0), self.lasmixbar.get_master())
self.submodules.dvisampler1 = dvisampler.DVISampler(platform.request("dvi_in", 1), self.lasmixbar.get_master())
self.submodules.dvisampler0 = dvisampler.DVISampler(platform.request("dvi_in", 2), self.lasmixbar.get_master())
self.submodules.dvisampler1 = dvisampler.DVISampler(platform.request("dvi_in", 3), self.lasmixbar.get_master())

def get_default_subtarget(platform):
if platform.name == "mixxeo":