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base repository: m-labs/migen
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head repository: m-labs/migen
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compare: 9deddbdfbc91
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Mar 24, 2014

  1. test/support: fix default ncycles

    jordens authored and sbourdeauducq committed Mar 24, 2014
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    7649028 View commit details
  2. Copy the full SHA
    9deddbd View commit details
Showing with 4 additions and 4 deletions.
  1. +1 −1 migen/test/support.py
  2. +3 −3 migen/test/test_cordic.py
2 changes: 1 addition & 1 deletion migen/test/support.py
Original file line number Diff line number Diff line change
@@ -17,6 +17,6 @@ def setUp(self, *args, **kwargs):
def test_to_verilog(self):
verilog.convert(self.tb)

def run_with(self, cb, ncycles=-1):
def run_with(self, cb, ncycles=None):
self.tb.callback = cb
run_simulation(self.tb, ncycles=ncycles)
6 changes: 3 additions & 3 deletions migen/test/test_cordic.py
Original file line number Diff line number Diff line change
@@ -44,9 +44,9 @@ def cb(tb, tbp):
xo = floor(xo*c*g)
yo = floor(yo*c*g)
zo = floor(zo*c/zm)
xo1 = s.rd(tb.dut.xo)
yo1 = s.rd(tb.dut.yo)
zo1 = s.rd(tb.dut.zo)
xo1 = tbp.dut.xo
yo1 = tbp.dut.yo
zo1 = tbp.dut.zo
print((xi, yi, zi), (xo, yo, zo), (xo1, yo1, zo1))
self.assertAlmostEqual(xo, xo1, delta=delta)
self.assertAlmostEqual(yo, yo1, delta=delta)