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base repository: m-labs/migen
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head repository: m-labs/migen
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compare: eb1417c5ed0d
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  • 2 commits
  • 3 files changed
  • 1 contributor

Commits on Aug 8, 2013

  1. fhdl: support for naming related signals

    Sebastien Bourdeauducq committed Aug 8, 2013
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    305c698 View commit details
  2. fhdl: move insert_resets to tools

    Sebastien Bourdeauducq committed Aug 8, 2013
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    eb1417c View commit details
Showing with 15 additions and 12 deletions.
  1. +5 −2 migen/fhdl/structure.py
  2. +9 −0 migen/fhdl/tools.py
  3. +1 −10 migen/fhdl/verilog.py
7 changes: 5 additions & 2 deletions migen/fhdl/structure.py
Original file line number Diff line number Diff line change
@@ -113,7 +113,7 @@ def __init__(self, v, n):
self.n = n

class Signal(Value):
def __init__(self, bits_sign=None, name=None, variable=False, reset=0, name_override=None, min=None, max=None):
def __init__(self, bits_sign=None, name=None, variable=False, reset=0, name_override=None, min=None, max=None, related=None):
from migen.fhdl.size import bits_for

Value.__init__(self)
@@ -139,7 +139,10 @@ def __init__(self, bits_sign=None, name=None, variable=False, reset=0, name_over
self.variable = variable # deprecated
self.reset = reset
self.name_override = name_override
self.backtrace = tracer.trace_back(name)
self.backtrace = []
if related is not None:
self.backtrace += related.backtrace
self.backtrace += tracer.trace_back(name)

def __repr__(self):
return "<Signal " + (self.backtrace[-1][0] or "anonymous") + " at " + hex(id(self)) + ">"
9 changes: 9 additions & 0 deletions migen/fhdl/tools.py
Original file line number Diff line number Diff line change
@@ -128,6 +128,15 @@ def generate_reset(rst, sl):
def insert_reset(rst, sl):
return [If(rst, *generate_reset(rst, sl)).Else(*sl)]

def insert_resets(f):
newsync = dict()
for k, v in f.sync.items():
if f.clock_domains[k].rst is not None:
newsync[k] = insert_reset(ResetSignal(k), v)
else:
newsync[k] = v
f.sync = newsync

class _Lowerer(NodeTransformer):
def __init__(self):
self.target_context = False
11 changes: 1 addition & 10 deletions migen/fhdl/verilog.py
Original file line number Diff line number Diff line change
@@ -201,15 +201,6 @@ def _printcomb(f, ns, display_run):
r += "\n"
return r

def _insert_resets(f):
newsync = dict()
for k, v in f.sync.items():
if f.clock_domains[k].rst is not None:
newsync[k] = insert_reset(ResetSignal(k), v)
else:
newsync[k] = v
f.sync = newsync

def _printsync(f, ns):
r = ""
for k, v in sorted(f.sync.items(), key=itemgetter(0)):
@@ -303,7 +294,7 @@ def convert(f, ios=None, name="top",
raise KeyError("Unresolved clock domain: '"+cd_name+"'")

f = lower_complex_slices(f)
_insert_resets(f)
insert_resets(f)
f = lower_basics(f)
fs, lowered_specials = _lower_specials(special_overrides, f.specials)
f += lower_basics(fs)