fallen · Jul 19, 2012 · Jul 19, 2012
Showing with 80 additions and 8 deletions.

+24 −0 lm32_cpu.v

+20 −3 lm32_icache.v

+1 −0 lm32_include.v

+35 −5 lm32_instruction_unit.v
diff --git a/lm32_cpu.v b/lm32_cpu.v
@@ -630,11 +630,32 @@ reg [`LM32_WORD_RNG] cc;                        // Cycle counter CSR
 reg [`LM32_WORD_RNG] csr_read_data_x;           // Data read from CSRs
 
 // To/from instruction unit
+`ifdef CFG_PIPELINE_TRACES
+wire [`LM32_PC_RNG] pc_a;
+`endif
 wire [`LM32_PC_RNG] pc_f;                       // PC of instruction in F stage
 wire [`LM32_PC_RNG] pc_d;                       // PC of instruction in D stage
 wire [`LM32_PC_RNG] pc_x;                       // PC of instruction in X stage
 wire [`LM32_PC_RNG] pc_m;                       // PC of instruction in M stage
 wire [`LM32_PC_RNG] pc_w;                       // PC of instruction in W stage
+
+`ifdef CFG_PIPELINE_TRACES
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+	if (~rst_i)
+	begin
+		if (~stall_a)
+			$display("[%t] Addressing inst @ 0x%08X", $time, pc_a);
+		if (~stall_f)
+			$display("[%t] Fetching   inst @ 0x%08X", $time, pc_f);
+		if (~stall_d)
+			$display("[%t] Decoding   inst @ 0x%08X", $time, pc_d);
+		if (~stall_x)
+			$display("[%t] Executing  inst @ 0x%08X", $time, pc_x);
+	end
+end
+`endif
+
 `ifdef CFG_TRACE_ENABLED
 reg [`LM32_PC_RNG] pc_c;                        // PC of last commited instruction
 `endif
@@ -866,6 +887,9 @@ lm32_instruction_unit #(
 `endif
     // ----- Outputs -------
     // To pipeline
+`ifdef CFG_PIPELINE_TRACES
+    .pc_a		    (pc_a),
+`endif
     .pc_f                   (pc_f),
     .pc_d                   (pc_d),
     .pc_x                   (pc_x),

diff --git a/lm32_icache.v b/lm32_icache.v
@@ -107,6 +107,9 @@ module lm32_icache (
     rst_i,    
     stall_a,
     stall_f,
+`ifdef CFG_MMU_ENABLED
+    stall_x,
+`endif
     address_a,
     address_f,
     read_enable_f,
@@ -210,6 +213,7 @@ input rst_i;                                        // Reset
 
 input stall_a;                                      // Stall instruction in A stage
 input stall_f;                                      // Stall instruction in F stage
+input stall_x;					    // Stall instruction in X stage
 
 input valid_d;                                      // Valid instruction in D stage
 input branch_predict_taken_d;                       // Instruction in D stage is a branch and is predicted taken
@@ -326,7 +330,7 @@ wire itlb_data_valid;
 wire [`LM32_ITLB_LOOKUP_RANGE] itlb_lookup;
 reg go_to_user_mode;
 reg go_to_user_mode_2;
-wire itlb_enabled;
+reg itlb_enabled;
 
 `endif
 
@@ -656,8 +660,6 @@ endgenerate
 
 `ifdef CFG_MMU_ENABLED
 
-assign itlb_enabled = csr_psw[`LM32_CSR_PSW_ITLBE];
-
 // Compute address to use to index into the ITLB data memory
 assign itlb_data_read_address = address_a[`LM32_ITLB_IDX_RNG];
 
@@ -762,6 +764,21 @@ begin
 	end
 end
 
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+	if (rst_i == `TRUE)
+	begin
+		itlb_enabled <= `FALSE;
+	end
+	else
+	begin
+		if (~stall_x)
+		begin
+			itlb_enabled <= csr_psw[`LM32_CSR_PSW_ITLBE];
+		end
+	end
+end
+
 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
 begin
 	if (rst_i == `TRUE)

diff --git a/lm32_include.v b/lm32_include.v
@@ -98,6 +98,7 @@
 //`define CFG_GDBSTUB_ENABLED
 `define CFG_RANDOM_WISHBONE_LATENCY
 //`define CFG_VERBOSE_DISPLAY_ENABLED
+//`define CFG_PIPELINE_TRACES
 `define CFG_UART_ENABLED
 
 // Enable MMU

diff --git a/lm32_instruction_unit.v b/lm32_instruction_unit.v
@@ -139,6 +139,9 @@ module lm32_instruction_unit (
 `endif
     // ----- Outputs -------
     // To pipeline
+`ifdef CFG_PIPELINE_TRACES
+    pc_a,
+`endif
     pc_f,
     pc_d,
     pc_x,
@@ -362,6 +365,9 @@ wire itlb_miss;
 /////////////////////////////////////////////////////
 
 reg [`LM32_PC_RNG] pc_a;                                // A stage PC
+`ifdef CFG_PIPELINE_TRACES
+output [`LM32_PC_RNG] pc_a;
+`endif
 
 `ifdef LM32_CACHE_ENABLED
 reg [`LM32_PC_RNG] restart_address;                     // Address to restart from after a cache miss  
@@ -484,6 +490,9 @@ lm32_icache #(
     .rst_i                  (rst_i),      
     .stall_a                (stall_a),
     .stall_f                (stall_f),
+`ifdef CFG_MMU_ENABLED
+    .stall_x		    (stall_x),
+`endif
     .branch_predict_taken_d (branch_predict_taken_d),
     .valid_d                (valid_d),
     .address_a              (pc_a),
@@ -543,27 +552,48 @@ begin
     // The request from the latest pipeline stage must take priority
 `ifdef CFG_DCACHE_ENABLED
     if (dcache_restart_request == `TRUE)
+    begin
+`ifdef CFG_PIPELINE_TRACES
+        $display("[%t] We restart to 0x%08X because of DCACHE", $time, restart_address);
+`endif
         pc_a = restart_address;
+    end
     else 
 `endif    
       if (branch_taken_m == `TRUE)
 	if ((branch_mispredict_taken_m == `TRUE) && (exception_m == `FALSE))
+        begin
+`ifdef CFG_PIPELINE_TRACES
+	  $display("[%t] Mispredict, goto pc_x == 0x%08X", $time, pc_x);
+`endif
 	  pc_a = pc_x;
+        end
 	else
-          pc_a = branch_target_m;
-`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
-      else if (branch_taken_x == `TRUE)
-        pc_a = branch_target_x;
+        begin
+`ifdef CFG_PIPELINE_TRACES
+          $display("[%t] Correctly predicted, goto branch_target_m == 0x%08X", $time, branch_target_m);
 `endif
+          pc_a = branch_target_m;
+        end
       else
 	if ( (valid_d == `TRUE) && (branch_predict_taken_d == `TRUE) )
+        begin
+`ifdef CFG_PIPELINE_TRACES
+          $display("[%t] We go to branch_predict_address_d == 0x%08X", $time, branch_predict_address_d);
+`endif
 	  pc_a = branch_predict_address_d;
+        end
 	else
 `ifdef CFG_ICACHE_ENABLED
           if (icache_restart_request == `TRUE)
+          begin
+`ifdef CFG_PIPELINE_TRACES
+            $display("[%t] We restart to 0x%08X because of ICACHE", $time, restart_address);
+`endif
             pc_a = restart_address;
+          end
 	  else 
-`endif        
+`endif
             pc_a = pc_f + 1'b1;
 end