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base repository: m-labs/migen
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  • 3 commits
  • 3 files changed
  • 1 contributor

Commits on Dec 12, 2013

  1. specials/Memory: allow for more flexibility in memory port signals

    Sebastien Bourdeauducq committed Dec 12, 2013
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    c13fe1b View commit details
  2. utils/misc: add gcd_multiple function to compute GCD or any number of…

    … integers
    Sebastien Bourdeauducq committed Dec 12, 2013
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    adffec3 View commit details
  3. fhdl/simplify: add FullMemoryWE decorator that splits memories to rem…

    …ove partial WEs
    Sebastien Bourdeauducq committed Dec 12, 2013
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    adda930 View commit details
Showing with 59 additions and 2 deletions.
  1. +41 −0 migen/fhdl/simplify.py
  2. +9 −2 migen/fhdl/specials.py
  3. +9 −0 migen/util/misc.py
41 changes: 41 additions & 0 deletions migen/fhdl/simplify.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,41 @@
from migen.fhdl.std import *
from migen.fhdl.specials import _MemoryPort
from migen.fhdl.decorators import ModuleDecorator
from migen.util.misc import gcd_multiple

class FullMemoryWE(ModuleDecorator):
def transform_fragment(self, f):
newspecials = set()

for orig in f.specials:
if not isinstance(orig, Memory):
newspecials.add(orig)
continue
global_granularity = gcd_multiple([p.we_granularity if p.we_granularity else orig.width for p in orig.ports])
if global_granularity == orig.width:
newspecials.add(orig) # nothing to do
else:
for i in range(orig.width//global_granularity):
if orig.init is None:
newinit = None
else:
newinit = [(v >> i*global_granularity) & (2**global_granularity - 1) for v in orig.init]
newmem = Memory(global_granularity, orig.depth, newinit, orig.name_override + "_grain" + str(i))
newspecials.add(newmem)
for port in orig.ports:
port_granularity = port.we_granularity if port.we_granularity else orig.width
newport = _MemoryPort(adr=port.adr,

dat_r=port.dat_r[i*global_granularity:(i+1)*global_granularity] if port.dat_r is not None else None,
we=port.we[i*port_granularity//global_granularity] if port.we is not None else None,
dat_w=port.dat_w[i*global_granularity:(i+1)*global_granularity] if port.dat_w is not None else None,

async_read=port.async_read,
re=port.re,
we_granularity=0,
mode=port.mode,
clock_domain=port.clock)
newmem.ports.append(newport)
newspecials.add(newport)

f.specials = newspecials
11 changes: 9 additions & 2 deletions migen/fhdl/specials.py
Original file line number Diff line number Diff line change
@@ -177,7 +177,10 @@ def __init__(self, adr, dat_r, we=None, dat_w=None,
self.re = re
self.we_granularity = we_granularity
self.mode = mode
self.clock = ClockSignal(clock_domain)
if isinstance(clock_domain, str):
self.clock = ClockSignal(clock_domain)
else:
self.clock = clock_domain

def iter_expressions(self):
for attr, target_context in [
@@ -231,7 +234,11 @@ def get_port(self, write_capable=False, async_read=False,
@staticmethod
def emit_verilog(memory, ns):
r = ""
gn = ns.get_name # usable instead of verilog_printexpr as ports contain only signals
def gn(e):
if isinstance(e, Memory):
return ns.get_name(e)
else:
return verilog_printexpr(ns, e)[0]
adrbits = bits_for(memory.depth-1)

r += "reg [" + str(memory.width-1) + ":0] " \
9 changes: 9 additions & 0 deletions migen/util/misc.py
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
from fractions import gcd
import collections

def flat_iteration(l):
@@ -26,3 +27,11 @@ def autotype(s):
except ValueError:
pass
return s

def gcd_multiple(numbers):
l = len(numbers)
if l == 1:
return numbers[0]
else:
s = l//2
return gcd(gcd_multiple(numbers[:s]), gcd_multiple(numbers[s:]))