Fix compilation with MMU disabled

fallen · fallen · commit e47289845eaf · 2012-10-24T21:22:45.000+02:00
diff --git a/lm32_cpu.v b/lm32_cpu.v
@@ -2196,9 +2196,11 @@ begin
     `LM32_CSR_JRX:  csr_read_data_x = jrx_csr_read_data;
 `endif
     `LM32_CSR_CFG2: csr_read_data_x = cfg2;
+`ifdef `LM32_MMU_ENABLED
     `LM32_CSR_TLB_VADDRESS: csr_read_data_x = load_store_csr_read_data_x;
     `LM32_CSR_TLB_PADDRESS: csr_read_data_x = instruction_csr_read_data_x;
     `LM32_CSR_PSW:	csr_read_data_x = lm32_csr_psw_reg;
+`endif
     default:        csr_read_data_x = {`LM32_WORD_WIDTH{1'bx}};
     endcase
 end
diff --git a/lm32_dcache.v b/lm32_dcache.v
@@ -284,6 +284,7 @@ reg [`LM32_DC_ADDR_OFFSET_RNG] refill_offset;           // Which word in cache l
 wire last_refill;                                       // Indicates when on last cycle of cache refill
 reg [`LM32_DC_TMEM_ADDR_RNG] flush_set;                 // Which set is currently being flushed
 
+`ifdef LM32_MMU_ENABLED
 wire [addr_dtlb_index_width-1:0] dtlb_data_read_address;
 wire [addr_dtlb_index_width-1:0] dtlb_data_write_address;
 wire dtlb_data_read_port_enable;
@@ -310,10 +311,11 @@ reg dtlb_miss_q = `FALSE;
 reg [`LM32_WORD_RNG] dtlb_miss_addr;
 wire dtlb_data_valid;
 wire [`LM32_DTLB_LOOKUP_RANGE] dtlb_lookup;
+assign kernel_mode = kernel_mode_reg;
+`endif
 
 genvar i, j;
 
-assign kernel_mode = kernel_mode_reg;
 
 /////////////////////////////////////////////////////
 // Functions
@@ -553,12 +555,17 @@ assign flushing = state[0];
 assign check = state[1];
 assign refill = state[2];
 
-assign miss = (~(|way_match)) && (load_q_m == `TRUE) && (stall_m == `FALSE) && (~dtlb_miss);
-assign stall_request = (check == `FALSE) || (dtlb_state == `LM32_TLB_STATE_FLUSH 
+assign miss = (~(|way_match)) && (load_q_m == `TRUE) && (stall_m == `FALSE)
+`ifdef CFG_MMU_ENABLED
+ 		&& (~dtlb_miss)
+`endif
+		;
+assign stall_request = (check == `FALSE) 
 `ifdef CFG_MMU_ENABLED
-			&& (dtlb_enabled == `TRUE)
+			|| (dtlb_state == `LM32_TLB_STATE_FLUSH 
+			&& (dtlb_enabled == `TRUE))
 `endif
-			);
+			;
 
 /////////////////////////////////////////////////////
 // Sequential logic
@@ -807,7 +814,10 @@ begin
 						dtlb_updating <= 0;
 						dtlb_state <= `LM32_TLB_STATE_CHECK;
 					end
-
+					default:
+					begin
+						$display("[ %t ] DTLB TLBVADDRESS stored 0x%08X", $time, csr_write_data);
+					end
 					endcase
 				end
 				else
diff --git a/lm32_icache.v b/lm32_icache.v
@@ -885,7 +885,7 @@ begin
 					`LM32_TLB_CTRL_INVALIDATE_ENTRY:
 					begin
 //`ifdef CFG_VERBOSE_DISPLAY_ENABLED
-						$display("it's an INVALIDATE ENTRY at %t", $time);
+						$display("[ %t ] ITLB TLBVADDRESS INVALIDATE ENTRY 0x%08X command [vaddr_reg == 0x%08X]", $time, csr_write_data, itlb_update_vaddr_csr_reg);
 //`endif
 						itlb_flushing <= 1;
 //						itlb_flush_set <= itlb_update_vaddr_csr_reg[`LM32_ITLB_IDX_RNG];
diff --git a/lm32_interrupt.v b/lm32_interrupt.v
@@ -266,7 +266,11 @@ begin
             else if (csr_write_enable == `TRUE)
             begin
                 // Handle wcsr write
-                if ((csr == `LM32_CSR_IE) || (csr == `LM32_CSR_PSW))
+                if ((csr == `LM32_CSR_IE)
+`ifdef `LM32_MMU_ENABLED
+		 || (csr == `LM32_CSR_PSW)
+`endif
+		)
                 begin
                     ie <= csr_write_data[0];
                     eie <= csr_write_data[1];
diff --git a/lm32_load_store_unit.v b/lm32_load_store_unit.v
@@ -172,9 +172,9 @@ input kill_x;                                           // Kill instruction in X
 input kill_m;                                           // Kill instruction in M stage
 input exception_m;                                      // An exception occured in the M stage
 input exception_x;                                      // An exception occured in the X stage
-input eret_q_x;
 
 `ifdef CFG_MMU_ENABLED
+input eret_q_x;
 input [`LM32_CSR_RNG] csr;				// CSR read/write index
 input [`LM32_WORD_RNG] csr_write_data;			// Data to write to specified CSR
 input csr_write_enable;					// CSR write enable
