tb: use default runner

Sebastien Bourdeauducq · Sebastien Bourdeauducq · commit f68fcef90cc9 · 2013-02-09T17:09:29.000+01:00
diff --git a/tb/asmicon/asmicon.py b/tb/asmicon/asmicon.py
@@ -1,7 +1,6 @@
 from migen.fhdl.structure import *
 from migen.bus.asmibus import *
 from migen.sim.generic import Simulator, TopLevel
-from migen.sim.icarus import Runner
 
 from milkymist.asmicon import *
 
@@ -33,7 +32,7 @@ def end_simulation(s):
 	fragment = dut.get_fragment() + initiator1.get_fragment() + initiator2.get_fragment() + \
 		logger.get_fragment() + \
 		Fragment(sim=[end_simulation])
-	sim = Simulator(fragment, Runner(), TopLevel("my.vcd"))
+	sim = Simulator(fragment, TopLevel("my.vcd"))
 	sim.run(700)
 
 main()
diff --git a/tb/asmicon/asmicon_wb.py b/tb/asmicon/asmicon_wb.py
@@ -1,7 +1,6 @@
 from migen.fhdl.structure import *
 from migen.bus import wishbone, wishbone2asmi, asmibus
 from migen.sim.generic import Simulator, TopLevel
-from migen.sim.icarus import Runner
 
 from milkymist.asmicon import *
 
@@ -41,7 +40,7 @@ def end_simulation(s):
 		conn.get_fragment() + \
 		logger.get_fragment() + \
 		Fragment(sim=[end_simulation])
-	sim = Simulator(fragment, Runner(), TopLevel("my.vcd"))
+	sim = Simulator(fragment, TopLevel("my.vcd"))
 	sim.run()
 
 main()
diff --git a/tb/asmicon/bankmachine.py b/tb/asmicon/bankmachine.py
@@ -1,7 +1,6 @@
 from migen.fhdl.structure import *
 from migen.bus.asmibus import *
 from migen.sim.generic import Simulator, TopLevel
-from migen.sim.icarus import Runner
 
 from milkymist.asmicon.bankmachine import *
 
@@ -42,7 +41,7 @@ def end_simulation(s):
 	fragment = hub.get_fragment() + initiator.get_fragment() + \
 		dut.get_fragment() + logger.get_fragment() + completer.get_fragment() + \
 		Fragment(sim=[end_simulation])
-	sim = Simulator(fragment, Runner(), TopLevel("my.vcd"))
+	sim = Simulator(fragment, TopLevel("my.vcd"))
 	sim.run()
 
 main()
diff --git a/tb/asmicon/refresher.py b/tb/asmicon/refresher.py
@@ -2,7 +2,6 @@
 
 from migen.fhdl.structure import *
 from migen.sim.generic import Simulator, TopLevel
-from migen.sim.icarus import Runner
 
 from milkymist.asmicon.refresher import *
 
@@ -44,7 +43,7 @@ def main():
 	logger = CommandLogger(dut.cmd)
 	granter = Granter(dut.req, dut.ack)
 	fragment = dut.get_fragment() + logger.get_fragment() + granter.get_fragment()
-	sim = Simulator(fragment, Runner())
+	sim = Simulator(fragment)
 	sim.run(400)
 
 main()
diff --git a/tb/asmicon/selector.py b/tb/asmicon/selector.py
@@ -3,7 +3,6 @@
 from migen.fhdl.structure import *
 from migen.bus.asmibus import *
 from migen.sim.generic import Simulator, TopLevel
-from migen.sim.icarus import Runner
 
 from milkymist.asmicon.bankmachine import _AddressSlicer, _SimpleSelector
 
@@ -71,7 +70,7 @@ def end_simulation(s):
 	fragment = hub.get_fragment() + sum([i.get_fragment() for i in initiators], Fragment()) + \
 		logger.get_fragment() + selector.get_fragment() + completer.get_fragment() + \
 		Fragment(sim=[end_simulation])
-	sim = Simulator(fragment, Runner(), TopLevel("my.vcd"))
+	sim = Simulator(fragment, TopLevel("my.vcd"))
 	sim.run()
 
 main()
diff --git a/tb/framebuffer/framebuffer.py b/tb/framebuffer/framebuffer.py
@@ -1,7 +1,6 @@
 from migen.fhdl.structure import *
 from migen.bus import asmibus
 from migen.sim.generic import Simulator
-from migen.sim.icarus import Runner
 
 from milkymist.framebuffer import *
 
@@ -13,7 +12,7 @@ def main():
 	dut = Framebuffer(1, port, True)
 	
 	fragment = hub.get_fragment() + dut.get_fragment()
-	sim = Simulator(fragment, Runner())
+	sim = Simulator(fragment)
 	
 	sim.run(1)
 	def csr_w(addr, d):
