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Commit 63c1d7e

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author
Sebastien Bourdeauducq
committedJan 26, 2014
New simulation API
·
0.9.20.1
1 parent 8f69d9b commit 63c1d7e

29 files changed

+407
-464
lines changed
 

Diff for: ‎examples/basic/graycounter.py

+7-7
Original file line numberDiff line numberDiff line change
@@ -2,18 +2,18 @@
22

33
from migen.fhdl.std import *
44
from migen.genlib.cdc import GrayCounter
5-
from migen.sim.generic import Simulator
5+
from migen.sim.generic import run_simulation
66

77
class TB(Module):
88
def __init__(self, width=3):
99
self.width = width
1010
self.submodules.gc = GrayCounter(self.width)
1111
self.prng = Random(7345)
1212

13-
def do_simulation(self, s):
14-
print("{0:0{1}b} CE={2} bin={3}".format(s.rd(self.gc.q),
15-
self.width, s.rd(self.gc.ce), s.rd(self.gc.q_binary)))
16-
s.wr(self.gc.ce, self.prng.getrandbits(1))
13+
def do_simulation(self, selfp):
14+
print("{0:0{1}b} CE={2} bin={3}".format(selfp.gc.q,
15+
self.width, selfp.gc.ce, selfp.gc.q_binary))
16+
selfp.gc.ce = self.prng.getrandbits(1)
1717

18-
sim = Simulator(TB())
19-
sim.run(35)
18+
if __name__ == "__main__":
19+
run_simulation(TB(), ncycles=35)

Diff for: ‎examples/dataflow/dma.py

+9-66
Original file line numberDiff line numberDiff line change
@@ -3,10 +3,10 @@
33
from migen.fhdl.std import *
44
from migen.flow.network import *
55
from migen.flow.transactions import *
6-
from migen.actorlib import dma_wishbone, dma_asmi
6+
from migen.actorlib import dma_wishbone
77
from migen.actorlib.sim import *
8-
from migen.bus import wishbone, asmibus
9-
from migen.sim.generic import Simulator
8+
from migen.bus import wishbone
9+
from migen.sim.generic import run_simulation
1010

1111
class MyModel:
1212
def read(self, address):
@@ -19,9 +19,6 @@ def __init__(self):
1919
def can_ack(self, bus):
2020
return self.prng.randrange(0, 2)
2121

22-
class MyModelASMI(MyModel, asmibus.TargetModel):
23-
pass
24-
2522
def adrgen_gen():
2623
for i in range(10):
2724
print("Address: " + hex(i))
@@ -73,9 +70,6 @@ def __init__(self):
7370
self.submodules.comp = CompositeActor(g)
7471
TBWishbone.__init__(self, self.reader)
7572

76-
def do_simulation(self, s):
77-
s.interrupt = self.adrgen.token_exchanger.done and not s.rd(self.comp.busy)
78-
7973
class TBWishboneWriter(TBWishbone):
8074
def __init__(self):
8175
self.trgen = SimTrGen(30)
@@ -85,65 +79,14 @@ def __init__(self):
8579
self.submodules.comp = CompositeActor(g)
8680
TBWishbone.__init__(self, self.writer)
8781

88-
def do_simulation(self, s):
89-
s.interrupt = self.trgen.token_exchanger.done and not s.rd(self.comp.busy)
90-
91-
class TBAsmi(Module):
92-
def __init__(self, nslots):
93-
self.submodules.hub = asmibus.Hub(32, 32)
94-
self.port = self.hub.get_port(nslots)
95-
self.hub.finalize()
96-
97-
self.submodules.peripheral = asmibus.Target(MyModelASMI(), self.hub)
98-
self.submodules.tap = asmibus.Tap(self.hub)
99-
100-
class TBAsmiReader(TBAsmi):
101-
def __init__(self, nslots):
102-
TBAsmi.__init__(self, nslots)
103-
104-
self.adrgen = SimAdrGen(32)
105-
self.reader = dma_asmi.Reader(self.port)
106-
self.dumper = SimDumper()
107-
g = DataFlowGraph()
108-
g.add_connection(self.adrgen, self.reader)
109-
g.add_connection(self.reader, self.dumper)
110-
self.submodules.comp = CompositeActor(g)
111-
112-
def do_simulation(self, s):
113-
s.interrupt = self.adrgen.token_exchanger.done and not s.rd(self.comp.busy)
114-
115-
class TBAsmiWriter(TBAsmi):
116-
def __init__(self, nslots):
117-
TBAsmi.__init__(self, nslots)
118-
119-
self.trgen = SimTrGen(32)
120-
self.writer = dma_asmi.Writer(self.port)
121-
g = DataFlowGraph()
122-
g.add_connection(self.trgen, self.writer)
123-
self.submodules.comp = CompositeActor(g)
124-
125-
def do_simulation(self, s):
126-
s.interrupt = self.trgen.token_exchanger.done and not s.rd(self.comp.busy)
127-
12882
def test_wb_reader():
12983
print("*** Testing Wishbone reader")
130-
Simulator(TBWishboneReader()).run()
84+
run_simulation(TBWishboneReader())
13185

13286
def test_wb_writer():
13387
print("*** Testing Wishbone writer")
134-
Simulator(TBWishboneWriter()).run()
135-
136-
def test_asmi_reader(nslots):
137-
print("*** Testing ASMI reader (nslots={})".format(nslots))
138-
Simulator(TBAsmiReader(nslots)).run()
139-
140-
def test_asmi_writer(nslots):
141-
print("*** Testing ASMI writer (nslots={})".format(nslots))
142-
Simulator(TBAsmiWriter(nslots)).run()
143-
144-
test_wb_reader()
145-
test_wb_writer()
146-
test_asmi_reader(1)
147-
test_asmi_reader(2)
148-
test_asmi_writer(1)
149-
test_asmi_writer(2)
88+
run_simulation(TBWishboneWriter())
89+
90+
if __name__ == "__main__":
91+
test_wb_reader()
92+
test_wb_writer()

Diff for: ‎examples/dataflow/misc.py

+3-6
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
from migen.flow.transactions import *
33
from migen.actorlib import misc
44
from migen.actorlib.sim import *
5-
from migen.sim.generic import Simulator
5+
from migen.sim.generic import run_simulation
66

77
def source_gen():
88
for i in range(10):
@@ -26,15 +26,12 @@ def __init__(self):
2626
self.sink = Sink([("value", 32)])
2727
SimActor.__init__(self, sink_gen())
2828

29-
def main():
29+
if __name__ == "__main__":
3030
source = SimSource()
3131
loop = misc.IntSequence(32)
3232
sink = SimSink()
3333
g = DataFlowGraph()
3434
g.add_connection(source, loop)
3535
g.add_connection(loop, sink)
3636
comp = CompositeActor(g)
37-
sim = Simulator(comp)
38-
sim.run(500)
39-
40-
main()
37+
run_simulation(comp, ncycles=500)

Diff for: ‎examples/dataflow/structuring.py

+3-5
Original file line numberDiff line numberDiff line change
@@ -7,8 +7,8 @@
77
from migen.flow.transactions import *
88
from migen.actorlib import structuring
99
from migen.actorlib.sim import *
10-
from migen.sim.generic import Simulator
1110
from migen.flow import perftools
11+
from migen.sim.generic import run_simulation
1212

1313
pack_factor = 5
1414
base_layout = [("value", 32)]
@@ -55,13 +55,11 @@ def __init__(self):
5555
self.submodules.comp = CompositeActor(self.g)
5656
self.submodules.reporter = perftools.DFGReporter(self.g)
5757

58-
def main():
58+
if __name__ == "__main__":
5959
tb = TB()
60-
sim = Simulator(tb).run(1000)
60+
run_simulation(tb, ncycles=1000)
6161

6262
g_layout = nx.spectral_layout(tb.g)
6363
nx.draw(tb.g, g_layout)
6464
nx.draw_networkx_edge_labels(tb.g, g_layout, tb.reporter.get_edge_labels())
6565
plt.show()
66-
67-
main()

Diff for: ‎examples/pytholite/basic.py

+5-7
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
from migen.flow.transactions import *
33
from migen.actorlib.sim import *
44
from migen.pytholite.compiler import Pytholite
5-
from migen.sim.generic import Simulator
5+
from migen.sim.generic import run_simulation
66
from migen.fhdl import verilog
77

88
layout = [("r", 32)]
@@ -16,15 +16,13 @@ def __init__(self):
1616
self.result = Source(layout)
1717
SimActor.__init__(self, number_gen(5))
1818

19-
def run_sim(ng):
19+
def run_ng_sim(ng):
2020
g = DataFlowGraph()
2121
d = Dumper(layout)
2222
g.add_connection(ng, d)
2323

2424
c = CompositeActor(g)
25-
sim = Simulator(c)
26-
sim.run(20)
27-
del sim
25+
run_simulation(c, ncycles=20)
2826

2927
def make_ng_pytholite():
3028
ng_pytholite = Pytholite(number_gen, 5)
@@ -35,11 +33,11 @@ def make_ng_pytholite():
3533
def main():
3634
print("Simulating native Python:")
3735
ng_native = SimNumberGen()
38-
run_sim(ng_native)
36+
run_ng_sim(ng_native)
3937

4038
print("Simulating Pytholite:")
4139
ng_pytholite = make_ng_pytholite()
42-
run_sim(ng_pytholite)
40+
run_ng_sim(ng_pytholite)
4341

4442
print("Converting Pytholite to Verilog:")
4543
ng_pytholite = make_ng_pytholite()

Diff for: ‎examples/pytholite/uio.py

+5-7
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66
from migen.genlib.ioo import UnifiedIOSimulation
77
from migen.pytholite.transel import Register
88
from migen.pytholite.compiler import Pytholite
9-
from migen.sim.generic import Simulator
9+
from migen.sim.generic import run_simulation
1010
from migen.fhdl.std import *
1111
from migen.fhdl import verilog
1212

@@ -39,10 +39,8 @@ def __init__(self, ng):
3939
self.submodules.intercon = wishbone.InterconnectPointToPoint(ng.wb, self.slave.bus)
4040
self.submodules.ca = CompositeActor(g)
4141

42-
def run_sim(ng):
43-
sim = Simulator(TestBench(ng))
44-
sim.run(50)
45-
del sim
42+
def run_ng_sim(ng):
43+
run_simulation(TestBench(ng), ncycles=50)
4644

4745
def add_interfaces(obj):
4846
obj.result = Source(layout)
@@ -54,12 +52,12 @@ def main():
5452
print("Simulating native Python:")
5553
ng_native = UnifiedIOSimulation(gen())
5654
add_interfaces(ng_native)
57-
run_sim(ng_native)
55+
run_ng_sim(ng_native)
5856

5957
print("Simulating Pytholite:")
6058
ng_pytholite = Pytholite(gen)
6159
add_interfaces(ng_pytholite)
62-
run_sim(ng_pytholite)
60+
run_ng_sim(ng_pytholite)
6361

6462
print("Converting Pytholite to Verilog:")
6563
ng_pytholite = Pytholite(gen)

Diff for: ‎examples/sim/abstract_transactions_lasmi.py

+5-12
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
from migen.fhdl.std import *
22
from migen.bus.transactions import *
33
from migen.bus import lasmibus
4-
from migen.sim.generic import Simulator
4+
from migen.sim.generic import run_simulation
55

66
def my_generator(n):
77
bank = n % 4
@@ -30,16 +30,9 @@ class TB(Module):
3030
def __init__(self):
3131
self.submodules.controller = lasmibus.Target(MyModel(), aw=4, dw=32, nbanks=4, req_queue_size=4,
3232
read_latency=4, write_latency=1)
33-
self.submodules.xbar = lasmibus.Crossbar([self.controller.bus], 4, 2)
34-
self.initiators = [lasmibus.Initiator(my_generator(n), bus) for n, bus in enumerate(self.xbar.masters)]
33+
self.submodules.xbar = lasmibus.Crossbar([self.controller.bus], 2)
34+
self.initiators = [lasmibus.Initiator(my_generator(n), self.xbar.get_master()) for n in range(4)]
3535
self.submodules += self.initiators
3636

37-
def do_simulation(self, s):
38-
s.interrupt = all(m.done for m in self.initiators)
39-
40-
def main():
41-
tb = TB()
42-
sim = Simulator(tb)
43-
sim.run()
44-
45-
main()
37+
if __name__ == "__main__":
38+
run_simulation(TB())

Diff for: ‎examples/sim/abstract_transactions_wb.py

+3-11
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
from migen.fhdl.std import *
44
from migen.bus.transactions import *
55
from migen.bus import wishbone
6-
from migen.sim.generic import Simulator
6+
from migen.sim.generic import run_simulation
77

88
# Our bus master.
99
# Python generators let us program bus transactions in an elegant sequential style.
@@ -53,16 +53,8 @@ def __init__(self):
5353
# Connect the master to the slave.
5454
self.submodules.intercon = wishbone.InterconnectPointToPoint(self.master.bus, self.slave.bus)
5555

56-
def do_simulation(self, s):
57-
# Terminate the simulation when the initiator is done (i.e. our generator is exhausted).
58-
s.interrupt = self.master.done
59-
60-
def main():
61-
tb = TB()
62-
sim = Simulator(tb)
63-
sim.run()
64-
65-
main()
56+
if __name__ == "__main__":
57+
run_simulation(TB())
6658

6759
# Output:
6860
# <TWrite adr:0x0 dat:0x0>

Diff for: ‎examples/sim/basic1.py

+6-13
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,5 @@
1-
# Copyright (C) 2012 Vermeer Manufacturing Co.
2-
# License: GPLv3 with additional permissions (see README).
3-
41
from migen.fhdl.std import *
5-
from migen.sim.generic import Simulator
2+
from migen.sim.generic import run_simulation
63

74
# Our simple counter, which increments at every cycle
85
# and prints its current value in simulation.
@@ -15,21 +12,17 @@ def __init__(self):
1512
self.sync += self.count.eq(self.count + 1)
1613

1714
# This function will be called at every cycle.
18-
def do_simulation(self, s):
15+
def do_simulation(self, selfp):
1916
# Simply read the count signal and print it.
2017
# The output is:
2118
# Count: 0
2219
# Count: 1
2320
# Count: 2
2421
# ...
25-
print("Count: " + str(s.rd(self.count)))
22+
print("Count: " + str(selfp.count))
2623

27-
def main():
24+
if __name__ == "__main__":
2825
dut = Counter()
29-
# We do not specify a top-level nor runner object, and use the defaults.
30-
sim = Simulator(dut)
31-
# Since we do not use sim.interrupt, limit the simulation
26+
# Since we do not use StopSimulation, limit the simulation
3227
# to some number of cycles.
33-
sim.run(20)
34-
35-
main()
28+
run_simulation(dut, ncycles=20)

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