m1crg: fix signal names

m-labs · Feb 13, 2013 · 7ad2f70 · 7ad2f70
1 parent 5649e88
commit 7ad2f70
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Showing 2 changed files with 4 additions and 4 deletions.
diff --git a/load.jtag b/load.jtag
@@ -2,4 +2,4 @@ cable milkymist
 detect
 instruction CFG_OUT  000100 BYPASS
 instruction CFG_IN   000101 BYPASS
-pld load build/soc.bit
+pld load build/top.bit
diff --git a/verilog/m1crg/m1crg.v b/verilog/m1crg/m1crg.v
@@ -204,7 +204,7 @@ ODDR2 #(
 	.INIT(1'b0),
 	.SRTYPE("SYNC")
 ) sd_clk_forward_p (
-	.Q(sd_clk_out_p),
+	.Q(ddr_clk_pad_p),
 	.C0(clk2x_270),
 	.C1(~clk2x_270),
 	.CE(1'b1),
@@ -218,7 +218,7 @@ ODDR2 #(
 	.INIT(1'b0),
 	.SRTYPE("SYNC")
 ) sd_clk_forward_n (
-	.Q(sd_clk_out_n),
+	.Q(ddr_clk_pad_n),
 	.C0(clk2x_270),
 	.C1(~clk2x_270),
 	.CE(1'b1),
@@ -233,7 +233,7 @@ ODDR2 #(
  */
 
 always @(posedge pllout4)
-	eth_clk_pad <= ~eth_clk_pad;
+	eth_phy_clk_pad <= ~eth_phy_clk_pad;
 
 /* Let the synthesizer insert the appropriate buffers */
 assign eth_rx_clk = eth_rx_clk_pad;