m-labs · Apr 5, 2014 · Apr 5, 2014 · Apr 5, 2014
Showing with 60 additions and 7 deletions.

+11 −7 mibuild/xilinx_ise.py

+49 −0 migen/genlib/fifo.py
diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py
@@ -125,7 +125,7 @@ def _is_valid_version(path, v):
 		return False
 
 def _run_ise(build_name, ise_path, source, mode, ngdbuild_opt,
-		bitgen_opt, ise_commands):
+		bitgen_opt, ise_commands, map_opt, par_opt):
 	if sys.platform == "win32" or sys.platform == "cygwin":
 		source = False
 	build_script_contents = "# Autogenerated by mibuild\nset -e\n"
@@ -148,12 +148,13 @@ def _run_ise(build_name, ise_path, source, mode, ngdbuild_opt,
 
 	build_script_contents += """
 ngdbuild {ngdbuild_opt} -uc {build_name}.ucf {build_name}.{ext} {build_name}.ngd
-map -ol high -w -o {build_name}_map.ncd {build_name}.ngd {build_name}.pcf
-par -ol high -w {build_name}_map.ncd {build_name}.ncd {build_name}.pcf
-bitgen {bitgen_opt} -w {build_name}.ncd {build_name}.bit
+map {map_opt} -o {build_name}_map.ncd {build_name}.ngd {build_name}.pcf
+par {par_opt} {build_name}_map.ncd {build_name}.ncd {build_name}.pcf
+bitgen {bitgen_opt} {build_name}.ncd {build_name}.bit
 """
 	build_script_contents = build_script_contents.format(build_name=build_name,
-			ngdbuild_opt=ngdbuild_opt, bitgen_opt=bitgen_opt, ext=ext)
+			ngdbuild_opt=ngdbuild_opt, bitgen_opt=bitgen_opt, ext=ext,
+			par_opt=par_opt, map_opt=map_opt)
 	build_script_contents += ise_commands.format(build_name=build_name)
 	build_script_file = "build_" + build_name + ".sh"
 	tools.write_to_file(build_script_file, build_script_contents)
@@ -187,8 +188,10 @@ class XilinxISEPlatform(GenericPlatform):
 -opt_mode SPEED
 -reduce_control_sets auto
 -register_balancing yes"""
+	map_opt = "-ol high -w"
+	par_opt = "-ol high -w"
 	ngdbuild_opt = ""
-	bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes"
+	bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w"
 	ise_commands = ""
 	def get_verilog(self, *args, special_overrides=dict(), **kwargs):
 		so = {
@@ -238,6 +241,7 @@ def build(self, fragment, build_dir="build", build_name="top",
 		tools.write_to_file(build_name + ".ucf", _build_ucf(named_sc, named_pc))
 		if run:
 			_run_ise(build_name, ise_path, source, isemode,
-					ngdbuild_opt, self.bitgen_opt, self.ise_commands)
+					ngdbuild_opt, self.bitgen_opt, self.ise_commands,
+					self.map_opt, self.par_opt)
 
 		os.chdir("..")
diff --git a/migen/genlib/fifo.py b/migen/genlib/fifo.py
@@ -132,6 +132,55 @@ def __init__(self, width_or_layout, depth):
 			self.readable.eq(self.level != 0)
 		]
 
+class SyncFIFOClassic(Module, _FIFOInterface):
+	def __init__(self, width_or_layout, depth):
+		_FIFOInterface.__init__(self, width_or_layout, depth)
+		self.submodules.fifo = fifo = SyncFIFO(width_or_layout, depth)
+
+		self.writable = fifo.writable
+		self.din_bits = fifo.din_bits
+		self.din = fifo.din
+		self.we = fifo.we
+		self.readable = fifo.readable
+		self.re = fifo.re
+		self.flush = fifo.flush
+		self.level = fifo.level
+
+		###
+
+		self.sync += [
+				If(self.re & self.readable,
+					self.dout_bits.eq(fifo.dout_bits),
+				)]
+
+class SyncFIFOBuffered(Module, _FIFOInterface):
+	def __init__(self, width_or_layout, depth):
+		_FIFOInterface.__init__(self, width_or_layout, depth)
+		self.submodules.fifo = fifo = SyncFIFOClassic(width_or_layout, depth)
+
+		self.writable = fifo.writable
+		self.din_bits = fifo.din_bits
+		self.din = fifo.din
+		self.we = fifo.we
+		self.dout_bits = fifo.dout_bits
+		self.dout = fifo.dout
+		self.flush = fifo.flush
+		self.level = fifo.level
+
+		###
+
+		self.comb += [
+				fifo.re.eq(fifo.readable & (~self.readable | self.re)),
+				]
+		self.sync += [
+				If(self.flush,
+					self.readable.eq(0),
+				).Elif(fifo.re,
+					self.readable.eq(1),
+				).Elif(self.re,
+					self.readable.eq(0),
+				)]
+
 class AsyncFIFO(Module, _FIFOInterface):
 	"""Asynchronous FIFO (first in, first out)