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base repository: m-labs/artiq
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head repository: m-labs/artiq
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compare: 5105b88302b4
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  • 2 commits
  • 8 files changed
  • 1 contributor

Commits on Oct 21, 2014

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    9a14081 View commit details
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    5105b88 View commit details
Showing with 65 additions and 17 deletions.
  1. +9 −0 artiq/coredevice/rtio.py
  2. +1 −0 artiq/coredevice/runtime.py
  3. +10 −1 artiq/coredevice/runtime_exceptions.py
  4. +23 −12 soc/artiqlib/rtio/core.py
  5. +2 −1 soc/runtime/exceptions.h
  6. +18 −3 soc/runtime/rtio.c
  7. +1 −0 soc/runtime/rtio.h
  8. +1 −0 soc/runtime/services.c
9 changes: 9 additions & 0 deletions artiq/coredevice/rtio.py
Original file line number Diff line number Diff line change
@@ -180,6 +180,15 @@ def gate_both(self, duration):
delay(duration)
self._set_value(0)

@kernel
def pileup_count(self):
"""Returns the number of pileup events (a system clock cycle with too
many input transitions) since the last call to this function for this
channel (or since the last RTIO reset).
"""
return syscall("rtio_pileup_count", self.channel)

@kernel
def count(self):
"""Poll the RTIO input during all the previously programmed gate
1 change: 1 addition & 0 deletions artiq/coredevice/runtime.py
Original file line number Diff line number Diff line change
@@ -18,6 +18,7 @@
"rtio_replace": "Iii:n",
"rtio_sync": "i:n",
"rtio_get": "i:I",
"rtio_pileup_count": "i:i",
"dds_program": "iiI:n",
}

11 changes: 10 additions & 1 deletion artiq/coredevice/runtime_exceptions.py
Original file line number Diff line number Diff line change
@@ -13,7 +13,8 @@ class OutOfMemory(RuntimeException):


class RTIOUnderflow(RuntimeException):
"""Raised when the CPU fails to submit a RTIO event early enough (with respect to the event's timestamp).
"""Raised when the CPU fails to submit a RTIO event early enough
(with respect to the event's timestamp).
"""
eid = 1
@@ -28,6 +29,14 @@ class RTIOSequenceError(RuntimeException):
eid = 2


class RTIOOverflow(RuntimeException):
"""Raised when at least one event could not be registered into the RTIO
input FIFO because it was full (CPU not reading fast enough).
"""
eid = 3


exception_map = {e.eid: e for e in globals().values()
if inspect.isclass(e)
and issubclass(e, RuntimeException)
35 changes: 23 additions & 12 deletions soc/artiqlib/rtio/core.py
Original file line number Diff line number Diff line change
@@ -71,15 +71,16 @@ def __init__(self, rbus, counter, fine_ts_width, fifo_depth):
self.readable = Signal()
self.re = Signal()
self.overflow = Signal()
self.pileup = Signal()
self.pileup_count = Signal(16)
self.pileup_reset = Signal()

# # #

timestamps = []
values = []
readables = []
overflows = []
pileups = []
pileup_counts = []
for n, chif in enumerate(rbus):
if hasattr(chif, "oe"):
sensitivity = Signal(2)
@@ -115,22 +116,29 @@ def __init__(self, rbus, counter, fine_ts_width, fifo_depth):
self.sync += If(fifo.we & ~fifo.writable, overflow.eq(1))
overflows.append(overflow)

pileup = Signal()
self.sync += If(chif.i_pileup, pileup.eq(1))
pileups.append(pileup)
pileup_count = Signal(16)
self.sync += \
If(self.pileup_reset & (self.sel == n),
pileup_count.eq(0)
).Elif(chif.i_pileup,
If(pileup_count != 2**16 - 1, # saturate
pileup_count.eq(pileup_count + 1)
)
)
pileup_counts.append(pileup_count)
else:
timestamps.append(0)
values.append(0)
readables.append(0)
overflows.append(0)
pileups.append(0)
pileup_counts.append(0)

self.comb += [
self.timestamp.eq(Array(timestamps)[self.sel]),
self.value.eq(Array(values)[self.sel]),
self.readable.eq(Array(readables)[self.sel]),
self.overflow.eq(Array(overflows)[self.sel]),
self.pileup.eq(Array(pileups)[self.sel])
self.pileup_count.eq(Array(pileup_counts)[self.sel])
]


@@ -171,14 +179,16 @@ def __init__(self, phy, clk_freq, counter_width=32, ofifo_depth=64, ififo_depth=
self._r_o_writable = CSRStatus()
self._r_o_we = CSR()
self._r_o_replace = CSR()
self._r_o_error = CSRStatus()
self._r_o_underflow = CSRStatus()
self._r_o_level = CSRStatus(bits_for(ofifo_depth))

self._r_i_timestamp = CSRStatus(counter_width+fine_ts_width)
self._r_i_value = CSRStatus()
self._r_i_readable = CSRStatus()
self._r_i_re = CSR()
self._r_i_error = CSRStatus(2)
self._r_i_overflow = CSRStatus()
self._r_i_pileup_count = CSRStatus(16)
self._r_i_pileup_reset = CSR()

self._r_counter = CSRStatus(counter_width+fine_ts_width)
self._r_counter_update = CSR()
@@ -209,7 +219,7 @@ def __init__(self, phy, clk_freq, counter_width=32, ofifo_depth=64, ififo_depth=
self._r_o_writable.status.eq(self.bank_o.writable),
self.bank_o.we.eq(self._r_o_we.re),
self.bank_o.replace.eq(self._r_o_replace.re),
self._r_o_error.status.eq(self.bank_o.underflow),
self._r_o_underflow.status.eq(self.bank_o.underflow),
self._r_o_level.status.eq(self.bank_o.level)
]

@@ -221,8 +231,9 @@ def __init__(self, phy, clk_freq, counter_width=32, ofifo_depth=64, ififo_depth=
self._r_i_value.status.eq(self.bank_i.value),
self._r_i_readable.status.eq(self.bank_i.readable),
self.bank_i.re.eq(self._r_i_re.re),
self._r_i_error.status.eq(
Cat(self.bank_i.overflow, self.bank_i.pileup))
self._r_i_overflow.status.eq(self.bank_i.overflow),
self._r_i_pileup_count.status.eq(self.bank_i.pileup_count),
self.bank_i.pileup_reset.eq(self._r_i_pileup_reset.re)
]

# Counter access
3 changes: 2 additions & 1 deletion soc/runtime/exceptions.h
Original file line number Diff line number Diff line change
@@ -4,7 +4,8 @@
enum {
EID_OUT_OF_MEMORY = 0,
EID_RTIO_UNDERFLOW = 1,
EID_RTIO_SEQUENCE_ERROR = 2
EID_RTIO_SEQUENCE_ERROR = 2,
EID_RTIO_OVERFLOW = 3,
};

int exception_setjmp(void *jb) __attribute__((returns_twice));
21 changes: 18 additions & 3 deletions soc/runtime/rtio.c
Original file line number Diff line number Diff line change
@@ -27,7 +27,7 @@ void rtio_set(long long int timestamp, int channel, int value)
rtio_o_value_write(value);
while(!rtio_o_writable_read());
rtio_o_we_write(1);
if(rtio_o_error_read()) {
if(rtio_o_underflow_read()) {
rtio_reset_logic_write(1);
rtio_reset_logic_write(0);
exception_raise(EID_RTIO_UNDERFLOW);
@@ -40,7 +40,7 @@ void rtio_replace(long long int timestamp, int channel, int value)
rtio_o_timestamp_write(timestamp);
rtio_o_value_write(value);
rtio_o_replace_write(1);
if(rtio_o_error_read()) {
if(rtio_o_underflow_read()) {
rtio_reset_logic_write(1);
rtio_reset_logic_write(0);
exception_raise(EID_RTIO_UNDERFLOW);
@@ -59,6 +59,11 @@ long long int rtio_get(int channel)

rtio_chan_sel_write(channel);
while(rtio_i_readable_read() || (rtio_o_level_read() != 0)) {
if(rtio_i_overflow_read()) {
rtio_reset_logic_write(1);
rtio_reset_logic_write(0);
exception_raise(EID_RTIO_OVERFLOW);
}
if(rtio_i_readable_read()) {
r = rtio_i_timestamp_read();
rtio_i_re_write(1);
@@ -68,6 +73,16 @@ long long int rtio_get(int channel)
return -1;
}

int rtio_pileup_count(int channel)
{
int r;

rtio_chan_sel_write(channel);
r = rtio_i_pileup_count_read();
rtio_i_pileup_reset_write(1);
return r;
}

#define RTIO_FUD_CHANNEL 4

void rtio_fud_sync(void)
@@ -96,7 +111,7 @@ void rtio_fud(long long int fud_time)
rtio_o_timestamp_write(fud_end_time);
rtio_o_value_write(0);
rtio_o_we_write(1);
if(rtio_o_error_read()) {
if(rtio_o_underflow_read()) {
rtio_reset_logic_write(1);
rtio_reset_logic_write(0);
exception_raise(EID_RTIO_UNDERFLOW);
1 change: 1 addition & 0 deletions soc/runtime/rtio.h
Original file line number Diff line number Diff line change
@@ -7,6 +7,7 @@ void rtio_set(long long int timestamp, int channel, int value);
void rtio_replace(long long int timestamp, int channel, int value);
void rtio_sync(int channel);
long long int rtio_get(int channel);
int rtio_pileup_count(int channel);

void rtio_fud_sync(void);
void rtio_fud(long long int fud_time);
1 change: 1 addition & 0 deletions soc/runtime/services.c
Original file line number Diff line number Diff line change
@@ -16,6 +16,7 @@ static const struct symbol syscalls[] = {
{"rtio_replace", rtio_replace},
{"rtio_sync", rtio_sync},
{"rtio_get", rtio_get},
{"rtio_pileup_count", rtio_pileup_count},
{"dds_program", dds_program},
{NULL, NULL}
};