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base repository: m-labs/misoc
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head repository: m-labs/misoc
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compare: d175e01876b4
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on May 5, 2013

  1. dvisampler/chansync: fix FIFO width

    Sebastien Bourdeauducq committed May 5, 2013
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    cb008a0 View commit details

  2. dvisampler: connect sync polarity detection

    Sebastien Bourdeauducq committed May 5, 2013
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    d175e01 View commit details
Showing with 12 additions and 11 deletions.
  1. +10 −9 milkymist/dvisampler/__init__.py
  2. +2 −2 milkymist/dvisampler/chansync.py
19 changes: 10 additions & 9 deletions milkymist/dvisampler/__init__.py
View file
Original file line number Diff line number Diff line change
@@ -10,6 +10,7 @@
from milkymist.dvisampler.charsync import CharSync
from milkymist.dvisampler.decoding import Decoding
from milkymist.dvisampler.chansync import ChanSync
from milkymist.dvisampler.syncpol import SyncPolarity
from milkymist.dvisampler.resdetection import ResolutionDetection

class DVISampler(Module, AutoCSR):
@@ -53,18 +54,18 @@ def __init__(self, pads):
self.chansync.data_in2.eq(self.data2_decod.output),
]

de = self.chansync.data_out0.de
r = self.chansync.data_out2.d
g = self.chansync.data_out1.d
b = self.chansync.data_out0.d
hsync = self.chansync.data_out0.c[0]
vsync = self.chansync.data_out0.c[1]
self.submodules.syncpol = SyncPolarity()
self.comb += [
self.syncpol.valid_i.eq(self.chansync.chan_synced),
self.syncpol.data_in0.eq(self.chansync.data_out0),
self.syncpol.data_in1.eq(self.chansync.data_out1),
self.syncpol.data_in2.eq(self.chansync.data_out2)
]

self.submodules.resdetection = ResolutionDetection()
self.comb += [
self.resdetection.de.eq(de),
self.resdetection.hsync.eq(hsync),
self.resdetection.vsync.eq(vsync)
self.resdetection.de.eq(self.syncpol.de),
self.resdetection.vsync.eq(self.syncpol.vsync)
]

class RawDVISampler(Module, AutoCSR):
4 changes: 2 additions & 2 deletions milkymist/dvisampler/chansync.py
View file
Original file line number Diff line number Diff line change
@@ -2,7 +2,7 @@
from migen.fhdl.module import Module
from migen.genlib.cdc import MultiReg
from migen.genlib.fifo import SyncFIFO
from migen.genlib.record import Record
from migen.genlib.record import Record, layout_len
from migen.genlib.misc import optree
from migen.bank.description import *

@@ -27,7 +27,7 @@ def __init__(self, nchan=3, depth=8):

###

fifo = SyncFIFO(10, depth)
fifo = SyncFIFO(layout_len(channel_layout), depth)
self.add_submodule(fifo, "pix")
self.comb += [
fifo.we.eq(self.valid_i),