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Commit dd6eacb

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author
Sebastien Bourdeauducq
committedOct 9, 2012
Remove uses of the RE signal on field registers
·
0.120.1
1 parent c86dd3c commit dd6eacb

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4 files changed

+70
-55
lines changed

4 files changed

+70
-55
lines changed
 

‎milkymist/dfii/__init__.py

+5-4
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@ def __init__(self, phase):
1515
self._rden = Field("rden", 1, WRITE_ONLY, READ_ONLY)
1616
self._command = RegisterFields("command",
1717
[self._cs, self._we, self._cas, self._ras, self._wren, self._rden])
18+
self._command_issue = RegisterRaw("command_issue")
1819

1920
self._address = RegisterField("address", len(self.phase.address))
2021
self._baddress = RegisterField("baddress", len(self.phase.bank))
@@ -23,13 +24,13 @@ def __init__(self, phase):
2324
self._rddata = RegisterField("rddata", len(self.phase.rddata), READ_ONLY, WRITE_ONLY)
2425

2526
def get_registers(self):
26-
return [self._command,
27+
return [self._command, self._command_issue,
2728
self._address, self._baddress,
2829
self._wrdata, self._rddata]
2930

3031
def get_fragment(self):
3132
comb = [
32-
If(self._command.re,
33+
If(self._command_issue.re,
3334
self.phase.cs_n.eq(~self._cs.r),
3435
self.phase.we_n.eq(~self._we.r),
3536
self.phase.cas_n.eq(~self._cas.r),
@@ -42,8 +43,8 @@ def get_fragment(self):
4243
),
4344
self.phase.address.eq(self._address.field.r),
4445
self.phase.bank.eq(self._baddress.field.r),
45-
self.phase.wrdata_en.eq(self._command.re & self._wren.r),
46-
self.phase.rddata_en.eq(self._command.re & self._rden.r),
46+
self.phase.wrdata_en.eq(self._command_issue.re & self._wren.r),
47+
self.phase.rddata_en.eq(self._command_issue.re & self._rden.r),
4748
self.phase.wrdata.eq(self._wrdata.field.r),
4849
self.phase.wrdata_mask.eq(0)
4950
]

‎milkymist/minimac3/__init__.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@ def __init__(self, address):
2626
self._rx_count_0 = RegisterField("rx_count_0", _count_width, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
2727
self._rx_count_1 = RegisterField("rx_count_1", _count_width, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
2828
self._tx_count = RegisterField("tx_count", _count_width, access_dev=READ_WRITE)
29-
self._tx_start = RegisterField("tx_start", access_bus=WRITE_ONLY)
29+
self._tx_start = RegisterRaw("tx_start")
3030
regs = [self._phy_reset, self._rx_count_0, self._rx_count_1, self._tx_count, self._tx_start]
3131

3232
self._rx_event_0 = EventSourcePulse()

‎software/bios/sdram.c

+22-10
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,18 @@ static void setaddr(int a)
2323
CSR_DFII_AL_P1 = a & 0x00ff;
2424
}
2525

26+
static void command_p0(int cmd)
27+
{
28+
CSR_DFII_COMMAND_P0 = cmd;
29+
CSR_DFII_COMMAND_ISSUE_P0 = 1;
30+
}
31+
32+
static void command_p1(int cmd)
33+
{
34+
CSR_DFII_COMMAND_P1 = cmd;
35+
CSR_DFII_COMMAND_ISSUE_P1 = 1;
36+
}
37+
2638
static void init_sequence(void)
2739
{
2840
int i;
@@ -34,33 +46,33 @@ static void init_sequence(void)
3446

3547
/* Precharge All */
3648
setaddr(0x0400);
37-
CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
49+
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
3850

3951
/* Load Extended Mode Register */
4052
CSR_DFII_BA_P0 = 1;
4153
setaddr(0x0000);
42-
CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
54+
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
4355
CSR_DFII_BA_P0 = 0;
4456

4557
/* Load Mode Register */
4658
setaddr(0x0132); /* Reset DLL, CL=3, BL=4 */
47-
CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
59+
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
4860
cdelay(200);
4961

5062
/* Precharge All */
5163
setaddr(0x0400);
52-
CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
64+
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
5365

5466
/* 2x Auto Refresh */
5567
for(i=0;i<2;i++) {
5668
setaddr(0);
57-
CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS;
69+
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS);
5870
cdelay(4);
5971
}
6072

6173
/* Load Mode Register */
6274
setaddr(0x0032); /* CL=3, BL=4 */
63-
CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
75+
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
6476
cdelay(200);
6577
}
6678

@@ -84,7 +96,7 @@ void ddrrow(char *_row)
8496
if(*_row == 0) {
8597
setaddr(0x0000);
8698
CSR_DFII_BA_P0 = 0;
87-
CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
99+
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
88100
cdelay(15);
89101
printf("Precharged\n");
90102
} else {
@@ -95,7 +107,7 @@ void ddrrow(char *_row)
95107
}
96108
setaddr(row);
97109
CSR_DFII_BA_P0 = 0;
98-
CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CS;
110+
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CS);
99111
cdelay(15);
100112
printf("Activated row %d\n", row);
101113
}
@@ -119,7 +131,7 @@ void ddrrd(char *startaddr)
119131

120132
setaddr(addr);
121133
CSR_DFII_BA_P0 = 0;
122-
CSR_DFII_COMMAND_P0 = DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA;
134+
command_p0(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA);
123135
cdelay(15);
124136

125137
for(i=0;i<8;i++)
@@ -152,7 +164,7 @@ void ddrwr(char *startaddr)
152164

153165
setaddr(addr);
154166
CSR_DFII_BA_P1 = 0;
155-
CSR_DFII_COMMAND_P1 = DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS|DFII_COMMAND_WRDATA;
167+
command_p1(DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS|DFII_COMMAND_WRDATA);
156168
}
157169

158170
#define TEST_SIZE (4*1024*1024)

‎software/include/hw/dfii.h

+42-40
Original file line numberDiff line numberDiff line change
@@ -12,46 +12,48 @@
1212
#define DFII_CONTROL_CKE 0x02
1313

1414
#define CSR_DFII_COMMAND_P0 DFII_CSR(0x04)
15-
#define CSR_DFII_AH_P0 DFII_CSR(0x08)
16-
#define CSR_DFII_AL_P0 DFII_CSR(0x0C)
17-
#define CSR_DFII_BA_P0 DFII_CSR(0x10)
18-
#define CSR_DFII_WD0_P0 DFII_CSR(0x14)
19-
#define CSR_DFII_WD1_P0 DFII_CSR(0x18)
20-
#define CSR_DFII_WD2_P0 DFII_CSR(0x1C)
21-
#define CSR_DFII_WD3_P0 DFII_CSR(0x20)
22-
#define CSR_DFII_WD4_P0 DFII_CSR(0x24)
23-
#define CSR_DFII_WD5_P0 DFII_CSR(0x28)
24-
#define CSR_DFII_WD6_P0 DFII_CSR(0x2C)
25-
#define CSR_DFII_WD7_P0 DFII_CSR(0x30)
26-
#define CSR_DFII_RD0_P0 DFII_CSR(0x34)
27-
#define CSR_DFII_RD1_P0 DFII_CSR(0x38)
28-
#define CSR_DFII_RD2_P0 DFII_CSR(0x3C)
29-
#define CSR_DFII_RD3_P0 DFII_CSR(0x40)
30-
#define CSR_DFII_RD4_P0 DFII_CSR(0x44)
31-
#define CSR_DFII_RD5_P0 DFII_CSR(0x48)
32-
#define CSR_DFII_RD6_P0 DFII_CSR(0x4C)
33-
#define CSR_DFII_RD7_P0 DFII_CSR(0x50)
34-
35-
#define CSR_DFII_COMMAND_P1 DFII_CSR(0x54)
36-
#define CSR_DFII_AH_P1 DFII_CSR(0x58)
37-
#define CSR_DFII_AL_P1 DFII_CSR(0x5C)
38-
#define CSR_DFII_BA_P1 DFII_CSR(0x60)
39-
#define CSR_DFII_WD0_P1 DFII_CSR(0x64)
40-
#define CSR_DFII_WD1_P1 DFII_CSR(0x68)
41-
#define CSR_DFII_WD2_P1 DFII_CSR(0x6C)
42-
#define CSR_DFII_WD3_P1 DFII_CSR(0x70)
43-
#define CSR_DFII_WD4_P1 DFII_CSR(0x74)
44-
#define CSR_DFII_WD5_P1 DFII_CSR(0x78)
45-
#define CSR_DFII_WD6_P1 DFII_CSR(0x7C)
46-
#define CSR_DFII_WD7_P1 DFII_CSR(0x80)
47-
#define CSR_DFII_RD0_P1 DFII_CSR(0x84)
48-
#define CSR_DFII_RD1_P1 DFII_CSR(0x88)
49-
#define CSR_DFII_RD2_P1 DFII_CSR(0x8C)
50-
#define CSR_DFII_RD3_P1 DFII_CSR(0x90)
51-
#define CSR_DFII_RD4_P1 DFII_CSR(0x94)
52-
#define CSR_DFII_RD5_P1 DFII_CSR(0x98)
53-
#define CSR_DFII_RD6_P1 DFII_CSR(0x9C)
54-
#define CSR_DFII_RD7_P1 DFII_CSR(0xA0)
15+
#define CSR_DFII_COMMAND_ISSUE_P0 DFII_CSR(0x08)
16+
#define CSR_DFII_AH_P0 DFII_CSR(0x0C)
17+
#define CSR_DFII_AL_P0 DFII_CSR(0x10)
18+
#define CSR_DFII_BA_P0 DFII_CSR(0x14)
19+
#define CSR_DFII_WD0_P0 DFII_CSR(0x18)
20+
#define CSR_DFII_WD1_P0 DFII_CSR(0x1C)
21+
#define CSR_DFII_WD2_P0 DFII_CSR(0x20)
22+
#define CSR_DFII_WD3_P0 DFII_CSR(0x24)
23+
#define CSR_DFII_WD4_P0 DFII_CSR(0x28)
24+
#define CSR_DFII_WD5_P0 DFII_CSR(0x2C)
25+
#define CSR_DFII_WD6_P0 DFII_CSR(0x30)
26+
#define CSR_DFII_WD7_P0 DFII_CSR(0x34)
27+
#define CSR_DFII_RD0_P0 DFII_CSR(0x38)
28+
#define CSR_DFII_RD1_P0 DFII_CSR(0x3C)
29+
#define CSR_DFII_RD2_P0 DFII_CSR(0x40)
30+
#define CSR_DFII_RD3_P0 DFII_CSR(0x44)
31+
#define CSR_DFII_RD4_P0 DFII_CSR(0x48)
32+
#define CSR_DFII_RD5_P0 DFII_CSR(0x4C)
33+
#define CSR_DFII_RD6_P0 DFII_CSR(0x50)
34+
#define CSR_DFII_RD7_P0 DFII_CSR(0x54)
35+
36+
#define CSR_DFII_COMMAND_P1 DFII_CSR(0x58)
37+
#define CSR_DFII_COMMAND_ISSUE_P1 DFII_CSR(0x5C)
38+
#define CSR_DFII_AH_P1 DFII_CSR(0x60)
39+
#define CSR_DFII_AL_P1 DFII_CSR(0x64)
40+
#define CSR_DFII_BA_P1 DFII_CSR(0x68)
41+
#define CSR_DFII_WD0_P1 DFII_CSR(0x6C)
42+
#define CSR_DFII_WD1_P1 DFII_CSR(0x70)
43+
#define CSR_DFII_WD2_P1 DFII_CSR(0x74)
44+
#define CSR_DFII_WD3_P1 DFII_CSR(0x78)
45+
#define CSR_DFII_WD4_P1 DFII_CSR(0x7C)
46+
#define CSR_DFII_WD5_P1 DFII_CSR(0x80)
47+
#define CSR_DFII_WD6_P1 DFII_CSR(0x84)
48+
#define CSR_DFII_WD7_P1 DFII_CSR(0x88)
49+
#define CSR_DFII_RD0_P1 DFII_CSR(0x8C)
50+
#define CSR_DFII_RD1_P1 DFII_CSR(0x90)
51+
#define CSR_DFII_RD2_P1 DFII_CSR(0x94)
52+
#define CSR_DFII_RD3_P1 DFII_CSR(0x98)
53+
#define CSR_DFII_RD4_P1 DFII_CSR(0x9C)
54+
#define CSR_DFII_RD5_P1 DFII_CSR(0xA0)
55+
#define CSR_DFII_RD6_P1 DFII_CSR(0xA4)
56+
#define CSR_DFII_RD7_P1 DFII_CSR(0xA8)
5557

5658
#define DFII_COMMAND_CS 0x01
5759
#define DFII_COMMAND_WE 0x02

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