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remove trailing whitespaces
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enjoy-digital authored and sbourdeauducq committed Oct 17, 2014
1 parent 22507b1 commit dbaeaf7
Showing 72 changed files with 350 additions and 350 deletions.
2 changes: 1 addition & 1 deletion examples/dataflow/dma.py
Original file line number Diff line number Diff line change
@@ -38,7 +38,7 @@ def dumper_gen():
class SimDumper(SimActor):
def __init__(self):
self.data = Sink([("d", 32)])
SimActor.__init__(self, dumper_gen())
SimActor.__init__(self, dumper_gen())

def trgen_gen():
for i in range(10):
6 changes: 3 additions & 3 deletions examples/dataflow/structuring.py
Original file line number Diff line number Diff line change
@@ -39,13 +39,13 @@ class TB(Module):
def __init__(self):
source = SimSource()
sink = SimSink()

# A tortuous way of passing integer tokens.
packer = structuring.Pack(base_layout, pack_factor)
to_raw = structuring.Cast(packed_layout, rawbits_layout)
from_raw = structuring.Cast(rawbits_layout, packed_layout)
unpacker = structuring.Unpack(pack_factor, base_layout)

self.g = DataFlowGraph()
self.g.add_connection(source, packer)
self.g.add_connection(packer, to_raw)
@@ -58,7 +58,7 @@ def __init__(self):
if __name__ == "__main__":
tb = TB()
run_simulation(tb, ncycles=1000)

g = nx.MultiDiGraph()
for u, v, edge in tb.g.edges_iter():
g.add_edge(u, v, **edge)
6 changes: 3 additions & 3 deletions examples/pytholite/basic.py
Original file line number Diff line number Diff line change
@@ -20,7 +20,7 @@ def run_ng_sim(ng):
g = DataFlowGraph()
d = Dumper(layout)
g.add_connection(ng, d)

c = CompositeActor(g)
run_simulation(c, ncycles=20)

@@ -34,11 +34,11 @@ def main():
print("Simulating native Python:")
ng_native = SimNumberGen()
run_ng_sim(ng_native)

print("Simulating Pytholite:")
ng_pytholite = make_ng_pytholite()
run_ng_sim(ng_pytholite)

print("Converting Pytholite to Verilog:")
ng_pytholite = make_ng_pytholite()
print(verilog.convert(ng_pytholite))
8 changes: 4 additions & 4 deletions examples/pytholite/uio.py
Original file line number Diff line number Diff line change
@@ -34,7 +34,7 @@ def __init__(self, ng):
g = DataFlowGraph()
d = Dumper(layout)
g.add_connection(ng, d)

self.submodules.slave = wishbone.Target(SlaveModel())
self.submodules.intercon = wishbone.InterconnectPointToPoint(ng.wb, self.slave.bus)
self.submodules.ca = CompositeActor(g)
@@ -51,14 +51,14 @@ def add_interfaces(obj):
def main():
print("Simulating native Python:")
ng_native = UnifiedIOSimulation(gen())
add_interfaces(ng_native)
add_interfaces(ng_native)
run_ng_sim(ng_native)

print("Simulating Pytholite:")
ng_pytholite = Pytholite(gen)
add_interfaces(ng_pytholite)
run_ng_sim(ng_pytholite)

print("Converting Pytholite to Verilog:")
ng_pytholite = Pytholite(gen)
add_interfaces(ng_pytholite)
4 changes: 2 additions & 2 deletions examples/sim/abstract_transactions_lasmi.py
Original file line number Diff line number Diff line change
@@ -9,7 +9,7 @@ def my_generator(n):
t = TWrite(4*bank+x, 0x1000*bank + 0x100*x)
yield t
print("{0}: Wrote in {1} cycle(s)".format(n, t.latency))

for x in range(4):
t = TRead(4*bank+x)
yield t
@@ -21,7 +21,7 @@ def read(self, bank, address):
r = 0x1000*bank + 0x100*address
#print("read from bank {0} address {1} -> {2:x}".format(bank, address, r))
return r

def write(self, bank, address, data, we):
print("write to bank {0} address {1:x} data {2:x}".format(bank, address, data))
assert(data == 0x1000*bank + 0x100*address)
4 changes: 2 additions & 2 deletions examples/sim/basic1.py
Original file line number Diff line number Diff line change
@@ -10,12 +10,12 @@ def __init__(self):
# At each cycle, increase the value of the count signal.
# We do it with convertible/synthesizable FHDL code.
self.sync += self.count.eq(self.count + 1)

# This function will be called at every cycle.
def do_simulation(self, selfp):
# Simply read the count signal and print it.
# The output is:
# Count: 0
# Count: 0
# Count: 1
# Count: 2
# ...
4 changes: 2 additions & 2 deletions examples/sim/basic2.py
Original file line number Diff line number Diff line change
@@ -11,7 +11,7 @@ def __init__(self):
self.count = Signal((37, True), reset=-5)

self.sync += If(self.ce, self.count.eq(self.count + 1))

def do_simulation(self, selfp):
# Only assert CE every second cycle.
# => each counter value is held for two cycles.
@@ -21,7 +21,7 @@ def do_simulation(self, selfp):
selfp.ce = 1
print("Cycle: " + str(selfp.simulator.cycle_counter) + " Count: " + \
str(selfp.count))

# Output is:
# Cycle: 0 Count: -5
# Cycle: 1 Count: -5
10 changes: 5 additions & 5 deletions examples/sim/fir.py
Original file line number Diff line number Diff line change
@@ -14,7 +14,7 @@ def __init__(self, coef, wsize=16):
self.wsize = wsize
self.i = Signal((self.wsize, True))
self.o = Signal((self.wsize, True))

###

muls = []
@@ -37,7 +37,7 @@ def __init__(self, coef, frequency):
self.frequency = frequency
self.inputs = []
self.outputs = []

def do_simulation(self, selfp):
f = 2**(self.fir.wsize - 1)
v = 0.1*cos(2*pi*self.frequency*selfp.simulator.cycle_counter)
@@ -48,7 +48,7 @@ def do_simulation(self, selfp):
if __name__ == "__main__":
# Compute filter coefficients with SciPy.
coef = signal.remez(30, [0, 0.1, 0.2, 0.4, 0.45, 0.5], [0, 1, 0])

# Simulate for different frequencies and concatenate
# the results.
in_signals = []
@@ -58,12 +58,12 @@ def do_simulation(self, selfp):
run_simulation(tb, ncycles=200)
in_signals += tb.inputs
out_signals += tb.outputs

# Plot data from the input and output waveforms.
plt.plot(in_signals)
plt.plot(out_signals)
plt.show()

# Print the Verilog source for the filter.
fir = FIR(coef)
print(verilog.convert(fir, ios={fir.i, fir.o}))
2 changes: 1 addition & 1 deletion examples/sim/memory.py
Original file line number Diff line number Diff line change
@@ -6,7 +6,7 @@ def __init__(self):
# Initialize the beginning of the memory with integers
# from 0 to 19.
self.specials.mem = Memory(16, 2**12, init=list(range(20)))

def do_simulation(self, selfp):
# Read the memory. Use the cycle counter as address.
value = selfp.mem[selfp.simulator.cycle_counter]
6 changes: 3 additions & 3 deletions mibuild/altera_quartus.py
Original file line number Diff line number Diff line change
@@ -11,7 +11,7 @@ def _format_constraint(c):
if isinstance(c, Pins):
return "set_location_assignment PIN_" + c.identifiers[0]
elif isinstance(c, IOStandard):
return "set_instance_assignment -name IO_STANDARD " + "\"" + c.name + "\""
return "set_instance_assignment -name IO_STANDARD " + "\"" + c.name + "\""
elif isinstance(c, Misc):
return c.misc

@@ -79,15 +79,15 @@ def build(self, fragment, build_dir="build", build_name="top",
if not isinstance(fragment, _Fragment):
fragment = fragment.get_fragment()
self.finalize(fragment)

v_src, named_sc, named_pc = self.get_verilog(fragment)
v_file = build_name + ".v"
tools.write_to_file(v_file, v_src)
sources = self.sources + [(v_file, "verilog")]
_build_files(self.device, sources, self.verilog_include_paths, named_sc, named_pc, build_name)
if run:
_run_quartus(build_name, quartus_path)

os.chdir("..")

def add_period_constraint(self, clk, period):
16 changes: 8 additions & 8 deletions mibuild/generic_platform.py
Original file line number Diff line number Diff line change
@@ -10,7 +10,7 @@

class ConstraintError(Exception):
pass

class Pins:
def __init__(self, *identifiers):
self.identifiers = []
@@ -43,7 +43,7 @@ def _lookup(description, name, number):
if resource[0] == name and (number is None or resource[1] == number):
return resource
raise ConstraintError("Resource not found: " + name + ":" + str(number))

def _resource_type(resource):
t = None
for element in resource[2:]:
@@ -107,10 +107,10 @@ def __init__(self, io, connectors):

def add_extension(self, io):
self.available.extend(io)

def request(self, name, number=None):
resource = _lookup(self.available, name, number)
rt = _resource_type(resource)
rt = _resource_type(resource)
if isinstance(rt, int):
obj = Signal(rt, name_override=resource[0])
else:
@@ -128,10 +128,10 @@ def lookup_request(self, name, number=None):
if resource[0] == name and (number is None or resource[1] == number):
return obj
raise ConstraintError("Resource not found: " + name + ":" + str(number))

def add_platform_command(self, command, **signals):
self.platform_commands.append((command, signals))

def get_io_signals(self):
r = set()
for resource, obj in self.matched:
@@ -140,7 +140,7 @@ def get_io_signals(self):
else:
r.update(obj.flatten())
return r

def get_sig_constraints(self):
r = []
for resource, obj in self.matched:
@@ -263,7 +263,7 @@ def _get_source(self, fragment, gen_fn):
def get_verilog(self, fragment, **kwargs):
return self._get_source(fragment, lambda f: verilog.convert(f, self.constraint_manager.get_io_signals(),
return_ns=True, create_clock_domains=False, **kwargs))

def get_edif(self, fragment, cell_library, vendor, device, **kwargs):
return self._get_source(fragment, lambda f: edif.convert(f, self.constraint_manager.get_io_signals(),
cell_library, vendor, device, return_ns=True, **kwargs))
14 changes: 7 additions & 7 deletions mibuild/platforms/de0nano.py
Original file line number Diff line number Diff line change
@@ -20,17 +20,17 @@

("key", 0, Pins("J15"), IOStandard("3.3-V LVTTL")),
("key", 1, Pins("E1"), IOStandard("3.3-V LVTTL")),

("sw", 0, Pins("M1"), IOStandard("3.3-V LVTTL")),
("sw", 1, Pins("T9"), IOStandard("3.3-V LVTTL")),
("sw", 1, Pins("T9"), IOStandard("3.3-V LVTTL")),
("sw", 2, Pins("B9"), IOStandard("3.3-V LVTTL")),
("sw", 3, Pins("M15"), IOStandard("3.3-V LVTTL")),

("serial", 0,
Subsignal("tx", Pins("D3"), IOStandard("3.3-V LVTTL")),
Subsignal("rx", Pins("C3"), IOStandard("3.3-V LVTTL"))
),

("sdram_clock", 0, Pins("R4"), IOStandard("3.3-V LVTTL")),
("sdram", 0,
Subsignal("a", Pins("P2 N5 N6 M8 P8 T7 N8 T6 R1 P1 N2 N1 L4")),
@@ -44,15 +44,15 @@
Subsignal("dm", Pins("R6","T5")),
IOStandard("3.3-V LVTTL")
),

("epcs", 0,
Subsignal("data0", Pins("H2")),
Subsignal("dclk", Pins("H1")),
Subsignal("ncs0", Pins("D2")),
Subsignal("asd0", Pins("C1")),
IOStandard("3.3-V LVTTL")
),

("i2c", 0,
Subsignal("sclk", Pins("F2")),
Subsignal("sdat", Pins("F1")),
@@ -64,15 +64,15 @@
Subsignal("int", Pins("M2")),
IOStandard("3.3-V LVTTL")
),

("adc", 0,
Subsignal("cs_n", Pins("A10")),
Subsignal("saddr", Pins("B10")),
Subsignal("sclk", Pins("B14")),
Subsignal("sdat", Pins("A9")),
IOStandard("3.3-V LVTTL")
),

("gpio_0", 0,
Pins("D3 C3 A2 A3 B3 B4 A4 B5 A5 D5 B6 A6 B7 D6 A7 C6",
"C8 E6 E7 D8 E8 F8 F9 E9 C9 D9 E11 E10 C11 B11 A12 D11",
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