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Commit 859c9d8

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author
Sebastien Bourdeauducq
committedFeb 15, 2012
Use new bus API
·
0.120.1
1 parent 1368b66 commit 859c9d8

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3 files changed

+42
-39
lines changed

3 files changed

+42
-39
lines changed
 

Diff for: ‎milkymist/lm32/__init__.py

+27-24
Original file line numberDiff line numberDiff line change
@@ -3,40 +3,43 @@
33

44
class LM32:
55
def __init__(self):
6-
self.ibus = i = wishbone.Master()
7-
self.dbus = d = wishbone.Master()
6+
self.ibus = i = wishbone.Interface()
7+
self.dbus = d = wishbone.Interface()
88
self.interrupt = Signal(BV(32))
99
self.ext_break = Signal()
1010
self._inst = Instance("lm32_top",
1111
[("I_ADR_O", BV(32)),
12-
("I_DAT_O", i.dat_o),
13-
("I_SEL_O", i.sel_o),
14-
("I_CYC_O", i.cyc_o),
15-
("I_STB_O", i.stb_o),
16-
("I_WE_O", i.we_o),
17-
("I_CTI_O", i.cti_o),
12+
("I_DAT_O", i.dat_w),
13+
("I_SEL_O", i.sel),
14+
("I_CYC_O", i.cyc),
15+
("I_STB_O", i.stb),
16+
("I_WE_O", i.we),
17+
("I_CTI_O", i.cti),
1818
("I_LOCK_O", BV(1)),
19-
("I_BTE_O", i.bte_o),
19+
("I_BTE_O", i.bte),
2020
("D_ADR_O", BV(32)),
21-
("D_DAT_O", d.dat_o),
22-
("D_SEL_O", d.sel_o),
23-
("D_CYC_O", d.cyc_o),
24-
("D_STB_O", d.stb_o),
25-
("D_WE_O", d.we_o),
26-
("D_CTI_O", d.cti_o),
21+
("D_DAT_O", d.dat_w),
22+
("D_SEL_O", d.sel),
23+
("D_CYC_O", d.cyc),
24+
("D_STB_O", d.stb),
25+
("D_WE_O", d.we),
26+
("D_CTI_O", d.cti),
2727
("D_LOCK_O", BV(1)),
28-
("D_BTE_O", d.bte_o)],
28+
("D_BTE_O", d.bte)],
29+
2930
[("interrupt", self.interrupt),
3031
#("ext_break", self.ext_break),
31-
("I_DAT_I", i.dat_i),
32-
("I_ACK_I", i.ack_i),
33-
("I_ERR_I", i.err_i),
32+
("I_DAT_I", i.dat_r),
33+
("I_ACK_I", i.ack),
34+
("I_ERR_I", i.err),
3435
("I_RTY_I", BV(1)),
35-
("D_DAT_I", d.dat_i),
36-
("D_ACK_I", d.ack_i),
37-
("D_ERR_I", d.err_i),
36+
("D_DAT_I", d.dat_r),
37+
("D_ACK_I", d.ack),
38+
("D_ERR_I", d.err),
3839
("D_RTY_I", BV(1))],
40+
3941
[],
42+
4043
"clk_i",
4144
"rst_i",
4245
"lm32")
@@ -45,7 +48,7 @@ def get_fragment(self):
4548
comb = [
4649
self._inst.ins["I_RTY_I"].eq(0),
4750
self._inst.ins["D_RTY_I"].eq(0),
48-
self.ibus.adr_o.eq(self._inst.outs["I_ADR_O"][2:]),
49-
self.dbus.adr_o.eq(self._inst.outs["D_ADR_O"][2:])
51+
self.ibus.adr.eq(self._inst.outs["I_ADR_O"][2:]),
52+
self.dbus.adr.eq(self._inst.outs["D_ADR_O"][2:])
5053
]
5154
return Fragment(comb=comb, instances=[self._inst])

Diff for: ‎milkymist/norflash/__init__.py

+8-8
Original file line numberDiff line numberDiff line change
@@ -4,22 +4,22 @@
44

55
class NorFlash:
66
def __init__(self, adr_width, rd_timing):
7-
self.bus = wishbone.Slave()
7+
self.bus = wishbone.Interface()
88
self.adr = Signal(BV(adr_width-1))
99
self.d = Signal(BV(16))
1010
self.oe_n = Signal()
1111
self.we_n = Signal()
1212
self.ce_n = Signal()
13-
self.timeline = timeline.Timeline(self.bus.cyc_i & self.bus.stb_i,
14-
[(0, [self.adr.eq(Cat(0, self.bus.adr_i[:adr_width-2]))]),
13+
self.timeline = timeline.Timeline(self.bus.cyc & self.bus.stb,
14+
[(0, [self.adr.eq(Cat(0, self.bus.adr[:adr_width-2]))]),
1515
(rd_timing, [
16-
self.bus.dat_o[16:].eq(self.d),
17-
self.adr.eq(Cat(1, self.bus.adr_i[:adr_width-2]))]),
16+
self.bus.dat_r[16:].eq(self.d),
17+
self.adr.eq(Cat(1, self.bus.adr[:adr_width-2]))]),
1818
(2*rd_timing, [
19-
self.bus.dat_o[:16].eq(self.d),
20-
self.bus.ack_o.eq(1)]),
19+
self.bus.dat_r[:16].eq(self.d),
20+
self.bus.ack.eq(1)]),
2121
(2*rd_timing+1, [
22-
self.bus.ack_o.eq(0)])])
22+
self.bus.ack.eq(0)])])
2323

2424
def get_fragment(self):
2525
comb = [self.oe_n.eq(0), self.we_n.eq(1),

Diff for: ‎milkymist/sram/__init__.py

+7-7
Original file line numberDiff line numberDiff line change
@@ -3,25 +3,25 @@
33

44
class SRAM:
55
def __init__(self, depth):
6-
self.bus = wishbone.Slave()
6+
self.bus = wishbone.Interface()
77
self.depth = depth
88

99
def get_fragment(self):
1010
# generate write enable signal
1111
we = Signal(BV(4))
12-
comb = [we[i].eq(self.bus.cyc_i & self.bus.stb_i & self.bus.we_i & self.bus.sel_i[i])
12+
comb = [we[i].eq(self.bus.cyc & self.bus.stb & self.bus.we & self.bus.sel[i])
1313
for i in range(4)]
1414
# split address
1515
nbits = bits_for(self.depth-1)
1616
partial_adr = Signal(BV(nbits))
17-
comb.append(partial_adr.eq(self.bus.adr_i[:nbits]))
17+
comb.append(partial_adr.eq(self.bus.adr[:nbits]))
1818
# generate ack
1919
sync = [
20-
self.bus.ack_o.eq(0),
21-
If(self.bus.cyc_i & self.bus.stb_i & ~self.bus.ack_o,
22-
self.bus.ack_o.eq(1)
20+
self.bus.ack.eq(0),
21+
If(self.bus.cyc & self.bus.stb & ~self.bus.ack,
22+
self.bus.ack.eq(1)
2323
)
2424
]
2525
# memory
26-
port = MemoryPort(partial_adr, self.bus.dat_o, we, self.bus.dat_i, we_granularity=8)
26+
port = MemoryPort(partial_adr, self.bus.dat_r, we, self.bus.dat_w, we_granularity=8)
2727
return Fragment(comb, sync, memories=[Memory(32, self.depth, port)])

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