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2 | 2 | from migen.flow.actor import * |
3 | 3 | from migen.flow.network import * |
4 | 4 | from migen.flow import plumbing |
5 | | -from migen.actorlib import misc, dma_asmi, structuring, sim |
| 5 | +from migen.actorlib import misc, dma_asmi, structuring, sim, spi |
6 | 6 | from migen.bank.description import * |
7 | 7 | from migen.bank import csrgen |
8 | 8 |
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|
27 | 27 | ("r", BV(_bpc_dac)) |
28 | 28 | ] |
29 | 29 |
|
30 | | -class _FrameInitiator(Actor): |
| 30 | +class _FrameInitiator(spi.SingleGenerator): |
31 | 31 | def __init__(self, asmi_bits, length_bits, alignment_bits): |
32 | | - self._alignment_bits = alignment_bits |
33 | | - |
34 | | - self._enable = RegisterField("enable") |
35 | | - |
36 | | - self._hres = RegisterField("hres", _hbits, reset=640) |
37 | | - self._hsync_start = RegisterField("hsync_start", _hbits, reset=656) |
38 | | - self._hsync_end = RegisterField("hsync_end", _hbits, reset=752) |
39 | | - self._hscan = RegisterField("hscan", _hbits, reset=799) |
40 | | - |
41 | | - self._vres = RegisterField("vres", _vbits, reset=480) |
42 | | - self._vsync_start = RegisterField("vsync_start", _vbits, reset=492) |
43 | | - self._vsync_end = RegisterField("vsync_end", _vbits, reset=494) |
44 | | - self._vscan = RegisterField("vscan", _vbits, reset=524) |
45 | | - |
46 | | - self._base = RegisterField("base", asmi_bits + self._alignment_bits) |
47 | | - self._length = RegisterField("length", length_bits + self._alignment_bits, reset=640*480*4) |
48 | | - |
49 | 32 | layout = [ |
50 | | - ("hres", BV(_hbits)), |
51 | | - ("hsync_start", BV(_hbits)), |
52 | | - ("hsync_end", BV(_hbits)), |
53 | | - ("hscan", BV(_hbits)), |
54 | | - ("vres", BV(_vbits)), |
55 | | - ("vsync_start", BV(_vbits)), |
56 | | - ("vsync_end", BV(_vbits)), |
57 | | - ("vscan", BV(_vbits)), |
58 | | - ("base", BV(asmi_bits)), |
59 | | - ("length", BV(length_bits)) |
60 | | - ] |
61 | | - super().__init__(("frame", Source, layout)) |
62 | | - |
63 | | - def get_registers(self): |
64 | | - return [self._enable, |
65 | | - self._hres, self._hsync_start, self._hsync_end, self._hscan, |
66 | | - self._vres, self._vsync_start, self._vsync_end, self._vscan, |
67 | | - self._base, self._length] |
68 | | - |
69 | | - def get_fragment(self): |
70 | | - # TODO: make address updates atomic |
71 | | - token = self.token("frame") |
72 | | - stb = self.endpoints["frame"].stb |
73 | | - ack = self.endpoints["frame"].ack |
74 | | - comb = [ |
75 | | - self.busy.eq(stb), |
76 | | - token.hres.eq(self._hres.field.r), |
77 | | - token.hsync_start.eq(self._hsync_start.field.r), |
78 | | - token.hsync_end.eq(self._hsync_end.field.r), |
79 | | - token.hscan.eq(self._hscan.field.r), |
80 | | - token.vres.eq(self._vres.field.r), |
81 | | - token.vsync_start.eq(self._vsync_start.field.r), |
82 | | - token.vsync_end.eq(self._vsync_end.field.r), |
83 | | - token.vscan.eq(self._vscan.field.r), |
84 | | - token.length.eq(self._length.field.r[self._alignment_bits:]) |
85 | | - ] |
86 | | - sync = [ |
87 | | - If(ack | ~stb, |
88 | | - stb.eq(self._enable.field.r), |
89 | | - token.base.eq(self._base.field.r[self._alignment_bits:]) |
90 | | - ) |
| 33 | + ("hres", BV(_hbits), 640), |
| 34 | + ("hsync_start", BV(_hbits), 656), |
| 35 | + ("hsync_end", BV(_hbits), 752), |
| 36 | + ("hscan", BV(_hbits), 799), |
| 37 | + |
| 38 | + ("vres", BV(_vbits), 480), |
| 39 | + ("vsync_start", BV(_vbits), 492), |
| 40 | + ("vsync_end", BV(_vbits), 494), |
| 41 | + ("vscan", BV(_vbits), 524), |
| 42 | + |
| 43 | + ("base", BV(asmi_bits), 0, alignment_bits), |
| 44 | + ("length", BV(length_bits), 640*480*4, alignment_bits) |
91 | 45 | ] |
92 | | - return Fragment(comb, sync) |
| 46 | + super().__init__(layout, spi.MODE_CONTINUOUS) |
93 | 47 |
|
94 | 48 | class VTG(Actor): |
95 | 49 | def __init__(self): |
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