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targets/ARTIQMiniSoC: map RTIO CSRs directly on Wishbone (reduces pro…
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…gramming time by 30%)
sbourdeauducq committed Nov 30, 2014
1 parent 1f64419 commit 7166ca8
Showing 1 changed file with 7 additions and 1 deletion.
8 changes: 7 additions & 1 deletion soc/targets/artiq.py
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
from migen.fhdl.std import *
from migen.bank import wbgen
from mibuild.generic_platform import *

from misoclib import gpio
@@ -70,7 +71,7 @@ def __init__(self, platform):

class ARTIQMiniSoC(BaseSoC):
csr_map = {
"rtio": 13
"rtio": None # mapped on Wishbone instead
}
csr_map.update(BaseSoC.csr_map)

@@ -101,6 +102,11 @@ def __init__(self, platform, cpu_type="or1k", ramcon_type="minicon",
clk_freq=125000000,
ififo_depth=512)

rtio_csrs = self.rtio.get_csrs()
self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
self.add_wb_slave(lambda a: a[26:29] == 2, self.rtiowb.bus)
self.add_cpu_csr_region("rtio", 0xa0000000, 32, rtio_csrs)

if with_test_gen:
self.submodules.test_gen = _TestGen(platform.request("ttl", 8))

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