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bank: support direct mapping of CSRs on Wishbone
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Original file line number | Diff line number | Diff line change |
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from migen.fhdl.std import Module, bits_for | ||
from migen.bank.description import CSR | ||
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class GenericBank(Module): | ||
def __init__(self, description, busword): | ||
# Turn description into simple CSRs and claim ownership of compound CSR modules | ||
self.simple_csrs = [] | ||
for c in description: | ||
if isinstance(c, CSR): | ||
self.simple_csrs.append(c) | ||
else: | ||
c.finalize(busword) | ||
self.simple_csrs += c.get_simple_csrs() | ||
self.submodules += c | ||
self.decode_bits = bits_for(len(self.simple_csrs)-1) | ||
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def get_offset(description, name, busword): | ||
offset = 0 | ||
for c in description: | ||
if c.name == name: | ||
return offset | ||
offset += (c.size + busword - 1)//busword | ||
raise KeyError("CSR not found: "+name) |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,26 @@ | ||
from migen.fhdl.std import * | ||
from migen.bus import wishbone | ||
from migen.bank.bank import GenericBank | ||
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class Bank(GenericBank): | ||
def __init__(self, description, bus=None): | ||
if bus is None: | ||
bus = wishbone.Interface() | ||
self.bus = bus | ||
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### | ||
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GenericBank.__init__(self, description, flen(self.bus.dat_w)) | ||
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for i, c in enumerate(self.simple_csrs): | ||
self.comb += [ | ||
c.r.eq(self.bus.dat_w[:c.size]), | ||
c.re.eq(self.bus.cyc & self.bus.stb & ~self.bus.ack & self.bus.we & \ | ||
(self.bus.adr[:self.decode_bits] == i)) | ||
] | ||
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brcases = dict((i, self.bus.dat_r.eq(c.w)) for i, c in enumerate(self.simple_csrs)) | ||
self.sync += [ | ||
Case(self.bus.adr[:self.decode_bits], brcases), | ||
If(bus.ack, bus.ack.eq(0)).Elif(bus.cyc & bus.stb, bus.ack.eq(1)) | ||
] |