New migen.fhdl.std to simplify imports + len->flen

m-labs · May 22, 2013 · 70ffe86 · 70ffe86
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Showing 61 changed files with 217 additions and 258 deletions.
diff --git a/examples/basic/arrays.py b/examples/basic/arrays.py
@@ -1,6 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Instance
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.fhdl import verilog
 
 class Example(Module):

diff --git a/examples/basic/complex.py b/examples/basic/complex.py
@@ -1,4 +1,4 @@
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.genlib.complex import *
 from migen.fhdl import verilog
 

diff --git a/examples/basic/fsm.py b/examples/basic/fsm.py
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.fhdl import verilog
 from migen.genlib.fsm import FSM
 

diff --git a/examples/basic/graycounter.py b/examples/basic/graycounter.py
@@ -1,6 +1,6 @@
 from random import Random
 
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.genlib.cdc import GrayCounter
 from migen.sim.generic import Simulator
 

diff --git a/examples/basic/local_cd.py b/examples/basic/local_cd.py
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.fhdl import verilog
 from migen.genlib.divider import Divider
 

diff --git a/examples/basic/memory.py b/examples/basic/memory.py
@@ -1,6 +1,4 @@
-from migen.fhdl.structure import Fragment
-from migen.fhdl.specials import Memory
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.fhdl import verilog
 
 class Example(Module):

diff --git a/examples/basic/namer.py b/examples/basic/namer.py
@@ -1,6 +1,5 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
 from migen.fhdl import verilog
-from migen.fhdl.module import Module
 from migen.genlib.misc import optree
 
 def gen_list(n):

diff --git a/examples/basic/psync.py b/examples/basic/psync.py
@@ -1,4 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
 from migen.fhdl.specials import SynthesisDirective
 from migen.fhdl import verilog
 from migen.genlib.cdc import *

diff --git a/examples/basic/record.py b/examples/basic/record.py
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.fhdl import verilog
 from migen.genlib.record import *
 

diff --git a/examples/basic/simple_gpio.py b/examples/basic/simple_gpio.py
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.fhdl import verilog
 from migen.genlib.cdc import MultiReg
 from migen.bank import description, csrgen

diff --git a/examples/basic/tristate.py b/examples/basic/tristate.py
@@ -1,16 +1,11 @@
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Tristate
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.fhdl import verilog
 
 class Example(Module):
 	def __init__(self, n=6):
 		self.pad = Signal(n)
-		self.o = Signal(n)
-		self.oe = Signal()
-		self.i = Signal(n)
-
-		self.specials += Tristate(self.pad, self.o, self.oe, self.i)
+		self.t = TSTriple(n)
+		self.specials += self.t.get_tristate(self.pad)
 
 e = Example()
-print(verilog.convert(e, ios={e.pad, e.o, e.oe, e.i}))
+print(verilog.convert(e, ios={e.pad, e.t.o, e.t.oe, e.t.i}))
diff --git a/examples/basic/two_dividers.py b/examples/basic/two_dividers.py
@@ -1,5 +1,5 @@
+from migen.fhdl.std import *
 from migen.fhdl import verilog
-from migen.fhdl.module import Module
 from migen.genlib import divider
 
 class Example(Module):

diff --git a/examples/dataflow/dma.py b/examples/dataflow/dma.py
@@ -1,6 +1,6 @@
 from random import Random
 
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.flow.network import *
 from migen.flow.transactions import *
 from migen.actorlib import dma_wishbone, dma_asmi

diff --git a/examples/pytholite/uio.py b/examples/pytholite/uio.py
@@ -7,8 +7,7 @@
 from migen.pytholite.transel import Register
 from migen.pytholite.compiler import Pytholite
 from migen.sim.generic import Simulator
-from migen.fhdl.module import Module
-from migen.fhdl.specials import Memory
+from migen.fhdl.std import *
 from migen.fhdl import verilog
 
 layout = [("r", 32)]

diff --git a/examples/sim/abstract_transactions.py b/examples/sim/abstract_transactions.py
@@ -1,10 +1,6 @@
-# Copyright (C) 2012 Vermeer Manufacturing Co.
-# License: GPLv3 with additional permissions (see README).
-
 from random import Random
 
-from migen.fhdl.structure import *
-from migen.fhdl import autofragment
+from migen.fhdl.std import *
 from migen.bus.transactions import *
 from migen.bus import wishbone, asmibus
 from migen.sim.generic import Simulator

diff --git a/examples/sim/basic1.py b/examples/sim/basic1.py
@@ -1,7 +1,7 @@
 # Copyright (C) 2012 Vermeer Manufacturing Co.
 # License: GPLv3 with additional permissions (see README).
 
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
 from migen.sim.generic import Simulator
 
 # Our simple counter, which increments at every cycle

diff --git a/examples/sim/basic2.py b/examples/sim/basic2.py
@@ -1,7 +1,7 @@
 # Copyright (C) 2012 Vermeer Manufacturing Co.
 # License: GPLv3 with additional permissions (see README).
 
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
 from migen.sim.generic import Simulator, TopLevel
 
 # A slightly improved counter.

diff --git a/examples/sim/dataflow.py b/examples/sim/dataflow.py
@@ -1,4 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
 from migen.flow.actor import *
 from migen.flow.transactions import *
 from migen.flow.network import *

diff --git a/examples/sim/fir.py b/examples/sim/fir.py
@@ -5,8 +5,7 @@
 from scipy import signal
 import matplotlib.pyplot as plt
 
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.fhdl import verilog
 from migen.genlib.misc import optree
 from migen.sim.generic import Simulator

diff --git a/examples/sim/memory.py b/examples/sim/memory.py
@@ -1,8 +1,7 @@
 # Copyright (C) 2012 Vermeer Manufacturing Co.
 # License: GPLv3 with additional permissions (see README).
 
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Memory
+from migen.fhdl.std import *
 from migen.sim.generic import Simulator
 
 class Mem:

diff --git a/migen/actorlib/dma_asmi.py b/migen/actorlib/dma_asmi.py
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.flow.actor import *
 from migen.genlib.buffers import ReorderBuffer
 
@@ -49,7 +48,7 @@ def __init__(self, port):
 
 		###
 
-		tag_width = len(port.tag_call)
+		tag_width = flen(port.tag_call)
 		data_width = port.hub.dw
 		depth = len(port.slots)
 		rob = ReorderBuffer(tag_width, data_width, depth)

diff --git a/migen/actorlib/dma_wishbone.py b/migen/actorlib/dma_wishbone.py
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.bus import wishbone
 from migen.flow.actor import *
 

diff --git a/migen/actorlib/misc.py b/migen/actorlib/misc.py
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.genlib.record import *
 from migen.genlib.fsm import *
 from migen.flow.actor import *

diff --git a/migen/actorlib/sim.py b/migen/actorlib/sim.py
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.flow.actor import *
 from migen.flow.transactions import *
 

diff --git a/migen/actorlib/spi.py b/migen/actorlib/spi.py
@@ -1,7 +1,6 @@
 # Simple Processor Interface
 
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Memory
+from migen.fhdl.std import *
 from migen.bank.description import *
 from migen.flow.actor import *
 from migen.flow.network import *
@@ -130,8 +129,8 @@ def get_csrs(self):
 
 class DMAReadController(_DMAController):
 	def __init__(self, bus_accessor, *args, **kwargs):
-		bus_aw = len(bus_accessor.address.payload.a)
-		bus_dw = len(bus_accessor.data.payload.d)
+		bus_aw = flen(bus_accessor.address.payload.a)
+		bus_dw = flen(bus_accessor.data.payload.d)
 		_DMAController.__init__(self, bus_accessor, bus_aw, bus_dw, *args, **kwargs)
 
 		g = DataFlowGraph()

diff --git a/migen/actorlib/structuring.py b/migen/actorlib/structuring.py
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.flow.actor import *
 
 def _rawbits_layout(l):
@@ -22,7 +21,7 @@ def __init__(self, layout_from, layout_to, reverse_from=False, reverse_to=False)
 		sigs_to = self.source.payload.flatten()
 		if reverse_to:
 			sigs_to = list(reversed(sigs_to))
-		if sum(len(s) for s in sigs_from) != sum(len(s) for s in sigs_to):
+		if sum(flen(s) for s in sigs_from) != sum(flen(s) for s in sigs_to):
 			raise TypeError
 		self.comb += Cat(*sigs_to).eq(Cat(*sigs_from))
 

diff --git a/migen/bank/csrgen.py b/migen/bank/csrgen.py
@@ -1,7 +1,6 @@
 from operator import itemgetter
 
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.bus import csr
 from migen.bank.description import *
 

diff --git a/migen/bank/description.py b/migen/bank/description.py
@@ -1,6 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Memory
-from migen.fhdl.module import *
+from migen.fhdl.std import *
 from migen.fhdl.tracer import get_obj_var_name
 
 class _CSRBase(HUID):

diff --git a/migen/bank/eventmanager.py b/migen/bank/eventmanager.py
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.bank.description import *
 from migen.genlib.misc import optree
 

diff --git a/migen/bus/asmibus.py b/migen/bus/asmibus.py
@@ -1,5 +1,5 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module, FinalizeError
+from migen.fhdl.std import *
+from migen.fhdl.module import FinalizeError
 from migen.genlib.misc import optree
 from migen.genlib import roundrobin
 from migen.bus.transactions import *

diff --git a/migen/bus/csr.py b/migen/bus/csr.py
@@ -1,6 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Memory
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.bus.transactions import *
 from migen.bank.description import CSRStorage
 from migen.genlib.record import *
@@ -115,10 +113,10 @@ def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None):
 				]
 
 		if self._page is None:
-			self.comb += port.adr.eq(self.bus.adr[word_bits:len(port.adr)])
+			self.comb += port.adr.eq(self.bus.adr[word_bits:flen(port.adr)])
 		else:
 			pv = self._page.storage
-			self.comb += port.adr.eq(Cat(self.bus.adr[word_bits:len(port.adr)-len(pv)], pv))
+			self.comb += port.adr.eq(Cat(self.bus.adr[word_bits:flen(port.adr)-flen(pv)], pv))
 
 	def get_csrs(self):
 		if self._page is None:

diff --git a/migen/bus/dfi.py b/migen/bus/dfi.py
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.genlib.record import *
 
 def phase_description(a, ba, d):

diff --git a/migen/bus/memory.py b/migen/bus/memory.py
@@ -1,4 +1,4 @@
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.bus.transactions import *
 
 def _byte_mask(orig, dat_w, sel):

diff --git a/migen/bus/transactions.py b/migen/bus/transactions.py
@@ -1,4 +1,4 @@
-from migen.fhdl.structure import bits_for
+from migen.fhdl.std import *
 
 class Transaction:
 	def __init__(self, address, data=0, sel=None, busname=None):

diff --git a/migen/bus/wishbone.py b/migen/bus/wishbone.py
@@ -1,6 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Memory
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.genlib import roundrobin
 from migen.genlib.record import *
 from migen.genlib.misc import optree
@@ -91,7 +89,7 @@ def __init__(self, master, slaves, register=False):
 		]
 
 		# mux (1-hot) slave data return
-		masked = [Replicate(slave_sel_r[i], len(master.dat_r)) & slaves[i][1].dat_r for i in range(ns)]
+		masked = [Replicate(slave_sel_r[i], flen(master.dat_r)) & slaves[i][1].dat_r for i in range(ns)]
 		self.comb += master.dat_r.eq(optree("|", masked))
 
 class InterconnectShared(Module):
@@ -210,7 +208,7 @@ def __init__(self, mem_or_size, read_only=None, init=None, bus=None):
 				for i in range(4)]
 		# address and data
 		self.comb += [
-			port.adr.eq(self.bus.adr[:len(port.adr)]),
+			port.adr.eq(self.bus.adr[:flen(port.adr)]),
 			self.bus.dat_r.eq(port.dat_r)
 		]
 		if not read_only:

diff --git a/migen/bus/wishbone2asmi.py b/migen/bus/wishbone2asmi.py
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Memory
+from migen.fhdl.std import *
 from migen.bus import wishbone
 from migen.genlib.fsm import FSM
 from migen.genlib.misc import split, displacer, chooser

diff --git a/migen/bus/wishbone2csr.py b/migen/bus/wishbone2csr.py
@@ -1,23 +1,23 @@
+from migen.fhdl.std import *
 from migen.bus import wishbone
 from migen.bus import csr
-from migen.fhdl.structure import *
 from migen.genlib.misc import timeline
 
-class WB2CSR:
+class WB2CSR(Module):
 	def __init__(self):
 		self.wishbone = wishbone.Interface()
 		self.csr = csr.Interface()
 
-	def get_fragment(self):
-		sync = [
+		###
+
+		self.sync += [
 			self.csr.we.eq(0),
 			self.csr.dat_w.eq(self.wishbone.dat_w[:csr.data_width]),
 			self.csr.adr.eq(self.wishbone.adr[:14]),
 			self.wishbone.dat_r.eq(self.csr.dat_r)
 		]
-		sync += timeline(self.wishbone.cyc & self.wishbone.stb, [
+		self.sync += timeline(self.wishbone.cyc & self.wishbone.stb, [
 			(1, [self.csr.we.eq(self.wishbone.we)]),
 			(2, [self.wishbone.ack.eq(1)]),
 			(3, [self.wishbone.ack.eq(0)])
 		])
-		return Fragment(sync=sync)