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genlib/fifo: support RecordP
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Sebastien Bourdeauducq committed Oct 21, 2013
1 parent 018afe5 commit c0d2b5a
Showing 1 changed file with 7 additions and 7 deletions.
14 changes: 7 additions & 7 deletions migen/genlib/fifo.py
Expand Up @@ -19,18 +19,18 @@ def __init__(self, width_or_layout, depth):
self.re = Signal()
self.readable = Signal() # not empty

if isinstance(width_or_layout, list):
self.din = Record(width_or_layout)
self.dout = Record(width_or_layout)
self.din_bits = self.din.raw_bits()
self.dout_bits = self.dout.raw_bits()
self.width = layout_len(width_or_layout)
else:
if isinstance(width_or_layout, (int, tuple)):
self.din = Signal(width_or_layout)
self.dout = Signal(width_or_layout)
self.din_bits = self.din
self.dout_bits = self.dout
self.width = width_or_layout
else:
self.din = Record(width_or_layout)
self.dout = Record(width_or_layout)
self.din_bits = self.din.raw_bits()
self.dout_bits = self.dout.raw_bits()
self.width = layout_len(width_or_layout)

class SyncFIFO(Module, _FIFOInterface):
def __init__(self, width_or_layout, depth):
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