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base repository: m-labs/misoc
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Dec 1, 2012

  1. Use Wishbone SRAM component from Migen

    Sebastien Bourdeauducq committed Dec 1, 2012
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    fee70e9 View commit details
  2. Merge branch 'master' of github.com:milkymist/milkymist-ng

    Sebastien Bourdeauducq committed Dec 1, 2012
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    bec02c4 View commit details
Showing with 2 additions and 31 deletions.
  1. +0 −29 milkymist/sram/__init__.py
  2. +2 −2 top.py
29 changes: 0 additions & 29 deletions milkymist/sram/__init__.py

This file was deleted.

4 changes: 2 additions & 2 deletions top.py
Original file line number Diff line number Diff line change
@@ -5,7 +5,7 @@
from migen.fhdl import verilog, autofragment
from migen.bus import wishbone, wishbone2asmi, csr, wishbone2csr, dfi

from milkymist import m1crg, lm32, norflash, uart, sram, s6ddrphy, dfii, asmicon, \
from milkymist import m1crg, lm32, norflash, uart, s6ddrphy, dfii, asmicon, \
identifier, timer, minimac3, framebuffer, asmiprobe
from cmacros import get_macros
from constraints import Constraints
@@ -81,7 +81,7 @@ def get():
#
cpu0 = lm32.LM32()
norflash0 = norflash.NorFlash(25, 12)
sram0 = sram.SRAM(sram_size//4)
sram0 = wishbone.SRAM(sram_size)
minimac0 = minimac3.MiniMAC(csr_offset("MINIMAC"))
wishbone2asmi0 = wishbone2asmi.WB2ASMI(l2_size//4, asmiport_wb)
wishbone2csr0 = wishbone2csr.WB2CSR()