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  • 5 commits
  • 12 files changed
  • 2 contributors

Commits on Feb 14, 2015

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    c7eba8f View commit details
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  5. endpoints: add param_layout parameter (required to pass parameter dat…

    …a with converters and will allow logic optimizations)
    enjoy-digital authored and sbourdeauducq committed Feb 14, 2015
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    452c60e View commit details
8 changes: 8 additions & 0 deletions doc/dataflow.rst
Original file line number Diff line number Diff line change
@@ -69,6 +69,14 @@ Accessing the endpoints is done by manipulating the signals inside the ``Source`
* A signal object ``ack``.
* The data payload ``payload``, which is a record with the layout given to the endpoint constructor.

Endpoints can also be used to manipulate packets, this is done by setting packetized parameter to True which adds:

* A signal object ``sop`` (Start Of Packet).
* A signal object ``eop`` (End Of Packet).

When used in packetized mode, packet parameters (signals that do no change for the duration of a packet) should to be declared in
param_layout. Declaring these signals in payload_layout will works in most cases but will prevent logic optimizations.

Busy signal
===========

13 changes: 0 additions & 13 deletions examples/basic/crc.py

This file was deleted.

5 changes: 4 additions & 1 deletion mibuild/altera_quartus.py
Original file line number Diff line number Diff line change
@@ -80,7 +80,8 @@ def build(self, fragment, build_dir="build", build_name="top",
fragment = fragment.get_fragment()
self.finalize(fragment)

v_src, named_sc, named_pc = self.get_verilog(fragment)
v_src, vns = self.get_verilog(fragment)
named_sc, named_pc = self.resolve_signals(vns)
v_file = build_name + ".v"
tools.write_to_file(v_file, v_src)
sources = self.sources + [(v_file, "verilog")]
@@ -90,6 +91,8 @@ def build(self, fragment, build_dir="build", build_name="top",

os.chdir("..")

return vns

def add_period_constraint(self, clk, period):
self.add_platform_command("""set_global_assignment -name DUTY_CYCLE 50 -section_id {clk}""", clk=clk)
self.add_platform_command("""set_global_assignment -name FMAX_REQUIREMENT "{freq} MHz" -section_id {clk}\n""".format(freq=str(float(1/period)*1000), clk="{clk}"), clk=clk)
5 changes: 2 additions & 3 deletions mibuild/generic_platform.py
Original file line number Diff line number Diff line change
@@ -240,7 +240,7 @@ def add_source_dir(self, path, recursive=True):
def add_verilog_include_path(self, path):
self.verilog_include_paths.append(os.path.abspath(path))

def _resolve_signals(self, vns):
def resolve_signals(self, vns):
# resolve signal names in constraints
sc = self.constraint_manager.get_sig_constraints()
named_sc = [(vns.get_name(sig), pins, others, resource) for sig, pins, others, resource in sc]
@@ -257,8 +257,7 @@ def _get_source(self, fragment, gen_fn):
fragment = fragment.get_fragment()
# generate source
src, vns = gen_fn(fragment)
named_sc, named_pc = self._resolve_signals(vns)
return src, named_sc, named_pc
return src, vns

def get_verilog(self, fragment, **kwargs):
return self._get_source(fragment, lambda f: verilog.convert(f, self.constraint_manager.get_io_signals(),
10 changes: 8 additions & 2 deletions mibuild/xilinx_ise.py
Original file line number Diff line number Diff line change
@@ -140,8 +140,11 @@ def build(self, fragment, build_dir="build", build_name="top",

ngdbuild_opt = self.ngdbuild_opt

vns = None

if mode == "xst" or mode == "yosys":
v_src, named_sc, named_pc = self.get_verilog(fragment)
v_src, vns = self.get_verilog(fragment)
named_sc, named_pc = self.resolve_signals(vns)
v_file = build_name + ".v"
tools.write_to_file(v_file, v_src)
sources = self.sources + [(v_file, "verilog")]
@@ -158,7 +161,8 @@ def build(self, fragment, build_dir="build", build_name="top",
synthesize(fragment, self.constraint_manager.get_io_signals())

if mode == "edif" or mode == "mist":
e_src, named_sc, named_pc = self.get_edif(fragment)
e_src, vns = self.get_edif(fragment)
named_sc, named_pc = self.resolve_signals(vns)
e_file = build_name + ".edif"
tools.write_to_file(e_file, e_src)
isemode = "edif"
@@ -171,6 +175,8 @@ def build(self, fragment, build_dir="build", build_name="top",

os.chdir("..")

return vns

def add_period_constraint(self, clk, period):
self.add_platform_command("""NET "{clk}" TNM_NET = "GRP{clk}";
TIMESPEC "TS{clk}" = PERIOD "GRP{clk}" """+str(period)+""" ns HIGH 50%;""", clk=clk)
5 changes: 4 additions & 1 deletion mibuild/xilinx_vivado.py
Original file line number Diff line number Diff line change
@@ -102,7 +102,8 @@ def build(self, fragment, build_dir="build", build_name="top",
if not isinstance(fragment, _Fragment):
fragment = fragment.get_fragment()
self.finalize(fragment)
v_src, named_sc, named_pc = self.get_verilog(fragment)
v_src, vns = self.get_verilog(fragment)
named_sc, named_pc = self.resolve_signals(vns)
v_file = build_name + ".v"
tools.write_to_file(v_file, v_src)
sources = self.sources + [(v_file, "verilog")]
@@ -114,6 +115,8 @@ def build(self, fragment, build_dir="build", build_name="top",

os.chdir("..")

return vns

def add_period_constraint(self, clk, period):
self.add_platform_command("""create_clock -name {clk} -period """ +\
str(period) + """ [get_ports {clk}]""", clk=clk)
171 changes: 0 additions & 171 deletions migen/actorlib/crc.py

This file was deleted.

10 changes: 9 additions & 1 deletion migen/actorlib/fifo.py
Original file line number Diff line number Diff line change
@@ -11,7 +11,13 @@ def __init__(self, fifo_class, layout, depth):
###

description = self.sink.description
fifo_layout = [("payload", description.payload_layout)]
fifo_layout = [
("payload", description.payload_layout),
# Note : Can be optimized by passing parameters
# in another fifo. We will only have one
# data per packet.
("param", description.param_layout)
]
if description.packetized:
fifo_layout += [("sop", 1), ("eop", 1)]

@@ -21,9 +27,11 @@ def __init__(self, fifo_class, layout, depth):
self.sink.ack.eq(self.fifo.writable),
self.fifo.we.eq(self.sink.stb),
self.fifo.din.payload.eq(self.sink.payload),
self.fifo.din.param.eq(self.sink.param),

self.source.stb.eq(self.fifo.readable),
self.source.payload.eq(self.fifo.dout.payload),
self.source.param.eq(self.fifo.dout.param),
self.fifo.re.eq(self.source.ack)
]
if description.packetized:
31 changes: 26 additions & 5 deletions migen/actorlib/structuring.py
Original file line number Diff line number Diff line change
@@ -66,6 +66,11 @@ def __init__(self, n, layout_to, reverse=False):
cases[i] = [source.payload.raw_bits().eq(getattr(sink.payload, "chunk"+str(chunk)).raw_bits())]
self.comb += Case(mux, cases).makedefault()

for f in description_from.param_layout:
src = getattr(self.sink, f[0])
dst = getattr(self.source, f[0])
self.comb += dst.eq(src)

if description_from.packetized:
self.comb += [
source.sop.eq(sink.sop & first),
@@ -97,6 +102,11 @@ def __init__(self, layout_from, n, reverse=False):
load_part.eq(sink.stb & sink.ack)
]

for f in description_to.param_layout:
src = getattr(self.sink, f[0])
dst = getattr(self.source, f[0])
self.comb += dst.eq(src)

if description_to.packetized:
demux_last = ((demux == (n - 1)) | sink.eop)
else:
@@ -118,11 +128,12 @@ def __init__(self, layout_from, n, reverse=False):
if description_to.packetized:
self.sync += [
If(source.stb & source.ack,
source.sop.eq(load_part & sink.sop)
).Else(
source.sop.eq((load_part & sink.sop) | source.sop)
),
source.eop.eq(load_part & sink.eop)
source.sop.eq(sink.sop),
source.eop.eq(sink.eop),
).Elif(sink.stb & sink.ack,
source.sop.eq(sink.sop | source.sop),
source.eop.eq(sink.eop | source.eop)
)
]

class Chunkerize(CombinatorialActor):
@@ -145,6 +156,11 @@ def __init__(self, layout_from, layout_to, n, reverse=False):
dst = getattr(getattr(self.source, "chunk"+str(chunk)), f[0])
self.comb += dst.eq(src[i*flen(src)//n:(i+1)*flen(src)//n])

for f in self.sink.description.param_layout:
src = getattr(self.sink, f[0])
dst = getattr(self.source, f[0])
self.comb += dst.eq(src)

class Unchunkerize(CombinatorialActor):
def __init__(self, layout_from, n, layout_to, reverse=False):
if isinstance(layout_from, EndpointDescription):
@@ -167,6 +183,11 @@ def __init__(self, layout_from, n, layout_to, reverse=False):
dst = getattr(self.source, f[0])
self.comb += dst[i*flen(dst)//n:(i+1)*flen(dst)//n].eq(src)

for f in self.sink.description.param_layout:
src = getattr(self.sink, f[0])
dst = getattr(self.source, f[0])
self.comb += dst.eq(src)

class Converter(Module):
def __init__(self, layout_from, layout_to, reverse=False):
self.sink = Sink(layout_from)
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