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base repository: m-labs/misoc
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Feb 14, 2015

  1. add setup.py

    enjoy-digital authored and sbourdeauducq committed Feb 14, 2015
    Copy the full SHA
    3559de9 View commit details
  2. gensoc: add csr_data_width and csr_address_width as parameters In som…

    …e case we want to have mode than 32 CSR or and csr_data_width != 8
    enjoy-digital authored and sbourdeauducq committed Feb 14, 2015
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    da13bd5 View commit details
Showing with 44 additions and 3 deletions.
  1. +7 −3 misoclib/gensoc/__init__.py
  2. +37 −0 setup.py
10 changes: 7 additions & 3 deletions misoclib/gensoc/__init__.py
Original file line number Diff line number Diff line change
@@ -33,12 +33,15 @@ class GenSoC(Module):
"kc705": 0x4B37
})

def __init__(self, platform, clk_freq, cpu_reset_address, sram_size=4096, l2_size=0, with_uart=True, cpu_type="lm32"):
def __init__(self, platform, clk_freq, cpu_reset_address, sram_size=4096, l2_size=0, with_uart=True, cpu_type="lm32",
csr_data_width=8, csr_address_width=14):
self.clk_freq = clk_freq
self.cpu_reset_address = cpu_reset_address
self.sram_size = sram_size
self.l2_size = l2_size
self.cpu_type = cpu_type
self.csr_data_width = csr_data_width
self.csr_address_width = csr_address_width
self.cpu_memory_regions = []
self.cpu_csr_regions = [] # list of (name, origin, busword, csr_list/Memory)
self._rom_registered = False
@@ -51,7 +54,7 @@ def __init__(self, platform, clk_freq, cpu_reset_address, sram_size=4096, l2_siz
else:
raise ValueError("Unsupported CPU type: "+cpu_type)
self.submodules.sram = wishbone.SRAM(sram_size)
self.submodules.wishbone2csr = wishbone2csr.WB2CSR()
self.submodules.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(csr_data_width, csr_address_width))

# rom 0x00000000 (shadow @0x80000000) from register_rom
# SRAM/debug 0x10000000 (shadow @0x90000000) provided
@@ -116,7 +119,8 @@ def do_finalize(self):

# CSR
self.submodules.csrbankarray = csrgen.BankArray(self,
lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override])
lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override],
data_width=self.csr_data_width, address_width=self.csr_address_width)
self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs)
37 changes: 37 additions & 0 deletions setup.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,37 @@
#!/usr/bin/env python3

import sys, os
from setuptools import setup
from setuptools import find_packages

here = os.path.abspath(os.path.dirname(__file__))
README = open(os.path.join(here, "README")).read()

required_version = (3, 3)
if sys.version_info < required_version:
raise SystemExit("MiSoC requires python {0} or greater".format(
".".join(map(str, required_version))))

setup(
name="misoclib",
version="unknown",
description="a high performance and small footprint SoC based on Migen",
long_description=README,
author="Sebastien Bourdeauducq",
author_email="sb@m-labs.hk",
url="http://m-labs.hk",
download_url="https://github.com/m-labs/misoc",
packages=find_packages(here),
license="BSD",
platforms=["Any"],
keywords="HDL ASIC FPGA hardware design",
classifiers=[
"Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
"Environment :: Console",
"Development Status :: Alpha",
"Intended Audience :: Developers",
"License :: OSI Approved :: BSD License",
"Operating System :: OS Independent",
"Programming Language :: Python",
],
)