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fhdl/verilog: improve error reporting
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Sebastien Bourdeauducq committed Jun 24, 2013
1 parent d6f7b4c commit b56cb3c
Showing 1 changed file with 2 additions and 2 deletions.
4 changes: 2 additions & 2 deletions migen/fhdl/verilog.py
Original file line number Diff line number Diff line change
@@ -80,7 +80,7 @@ def _printexpr(ns, node):
elif isinstance(node, Replicate):
return "{" + str(node.n) + "{" + _printexpr(ns, node.v)[0] + "}}", False
else:
raise TypeError
raise TypeError("Expression of unrecognized type: "+str(type(node)))

(_AT_BLOCKING, _AT_NONBLOCKING, _AT_SIGNAL) = range(3)

@@ -124,7 +124,7 @@ def _printnode(ns, at, level, node):
else:
return ""
else:
raise TypeError
raise TypeError("Node of unrecognized type: "+str(type(node)))

def _list_comb_wires(f):
r = set()

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