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Commit 7e76854

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committedOct 24, 2012
Fix typo
1 parent e472898 commit 7e76854

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3 files changed

+3
-3
lines changed

3 files changed

+3
-3
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‎lm32_cpu.v

+1-1
Original file line numberDiff line numberDiff line change
@@ -2196,7 +2196,7 @@ begin
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`LM32_CSR_JRX: csr_read_data_x = jrx_csr_read_data;
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`endif
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`LM32_CSR_CFG2: csr_read_data_x = cfg2;
2199-
`ifdef `LM32_MMU_ENABLED
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`ifdef CFG_MMU_ENABLED
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`LM32_CSR_TLB_VADDRESS: csr_read_data_x = load_store_csr_read_data_x;
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`LM32_CSR_TLB_PADDRESS: csr_read_data_x = instruction_csr_read_data_x;
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`LM32_CSR_PSW: csr_read_data_x = lm32_csr_psw_reg;

‎lm32_dcache.v

+1-1
Original file line numberDiff line numberDiff line change
@@ -284,7 +284,7 @@ reg [`LM32_DC_ADDR_OFFSET_RNG] refill_offset; // Which word in cache l
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wire last_refill; // Indicates when on last cycle of cache refill
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reg [`LM32_DC_TMEM_ADDR_RNG] flush_set; // Which set is currently being flushed
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287-
`ifdef LM32_MMU_ENABLED
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`ifdef CFG_MMU_ENABLED
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wire [addr_dtlb_index_width-1:0] dtlb_data_read_address;
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wire [addr_dtlb_index_width-1:0] dtlb_data_write_address;
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wire dtlb_data_read_port_enable;

‎lm32_interrupt.v

+1-1
Original file line numberDiff line numberDiff line change
@@ -267,7 +267,7 @@ begin
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begin
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// Handle wcsr write
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if ((csr == `LM32_CSR_IE)
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`ifdef `LM32_MMU_ENABLED
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`ifdef CFG_MMU_ENABLED
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|| (csr == `LM32_CSR_PSW)
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`endif
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)

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