uart: new design using FHDL and bank (TX only, incomplete)

m-labs · Dec 17, 2011 · 6664af7 · 6664af7
1 parent bb21f75
commit 6664af7
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Showing 5 changed files with 52 additions and 332 deletions.
diff --git a/build.py b/build.py
@@ -17,7 +17,6 @@ def add_core_files(d, files):
 	"lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
 	"lm32_dcache.v", "lm32_top.v", "lm32_debug.v", "lm32_jtag.v", "jtag_cores.v",
 	"jtag_tap_spartan6.v"])
-add_core_dir("uart")
 
 os.system("rm -rf build/*")
 os.chdir("build")

diff --git a/milkymist/uart/__init__.py b/milkymist/uart/__init__.py
@@ -1,28 +1,56 @@
+from functools import partial
+
 from migen.fhdl.structure import *
-from migen.bus import csr
+from migen.bank.description import *
+from migen.bank import csrgen
 
 class Inst:
-	def __init__(self, csr_addr, clk_freq, baud=115200, break_en_default=Constant(0)):
-		self.bus = csr.Slave("uart")
-		declare_signal(self, "tx")
-		declare_signal(self, "rx")
-		declare_signal(self, "irq")
-		declare_signal(self, "brk")
-		self._inst = Instance("uart",
-			[("csr_do", self.bus.d_o),
-			("uart_tx", self.tx),
-			("irq", self.irq),
-			("break", self.brk)],
-			[("csr_a", self.bus.a_i),
-			("csr_we", self.bus.we_i),
-			("csr_di", self.bus.d_i),
-			("uart_rx", self.rx)],
-			[("csr_addr", Constant(csr_addr, BV(5))),
-			("clk_freq", clk_freq),
-			("baud", baud),
-			("break_en_default", break_en_default)],
-			"sys_clk",
-			"sys_rst")
+	def __init__(self, address, clk_freq, baud=115200):
+		self._rxtx = rxtx = Register("rxtx", BV(8))
+		divisor = Register("divisor")
+		self._f_divisor = Field(divisor, "divisor", 8) # TODO: 16
+		stat = Register("stat") # TODO: autogenerated event manager
+		self._f_thre = Field(stat, "thre", access_bus=READ_ONLY, access_dev=WRITE_ONLY)
+
+		self.bank = csrgen.Bank([rxtx, divisor, stat], address=address)
+		d = partial(declare_signal, self)
+		d("tx", reset=1)
+		d("rx")
+
+		d("_enable16")
+		d("_enable16_counter", BV(16))
+		d("_tx_reg", BV(8))
+		d("_tx_bitcount", BV(4))
+		d("_tx_count16", BV(4))
+		d("_tx_busy")
+		self.divisor = int(clk_freq/baud/16); # TODO
 
 	def get_fragment(self):
-		return Fragment(instances=[self._inst], pads={self.tx, self.rx})
+		comb = [self._enable16.eq(self._enable16_counter == Constant(0, BV(16)))]
+		sync = [self._enable16_counter.eq(self._enable16_counter - 1),
+			If(self._enable16, self._enable16_counter.eq(self.divisor - 1))] # TODO
+
+		sync += [If(self._rxtx.dev_re,
+			self._tx_reg.eq(self._rxtx.dev_r),
+			self._tx_bitcount.eq(0),
+			self._tx_count16.eq(1),
+			self._tx_busy.eq(1),
+			self.tx.eq(0)
+		).Elif(self._enable16 & self._tx_busy,
+			self._tx_count16.eq(self._tx_count16 + 1),
+			If(self._tx_count16 == Constant(0, BV(4)),
+				self._tx_bitcount.eq(self._tx_bitcount + 1),
+				If(self._tx_bitcount == 8,
+					self.tx.eq(1)
+				).Elif(self._tx_bitcount == 9,
+					self.tx.eq(1),
+					self._tx_busy.eq(0)
+				).Else(
+					self.tx.eq(self._tx_reg[0]),
+					self._tx_reg.eq(Cat(self._tx_reg[1:], 0))
+				)
+			)
+		)]
+
+		comb += [self._f_thre.dev_we.eq(1), self._f_thre.dev_w.eq(~self._tx_busy)]
+		return self.bank.get_fragment() + Fragment(comb, sync, pads={self.tx, self.rx})
diff --git a/top.py b/top.py
@@ -21,7 +21,7 @@ def get():
 		register=True,
 		offset=1)
 	uart0 = uart.Inst(0, clk_freq, baud=115200)
-	csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bus])
+	csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bank.interface])
 
 	frag = autofragment.from_local()
 	vns = convtools.Namespace()

diff --git a/verilog/uart/uart.v b/verilog/uart/uart.v