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  • 2 commits
  • 11 files changed
  • 1 contributor

Commits on Jul 4, 2013

  1. dvisampler: support differential input

    Sebastien Bourdeauducq committed Jul 4, 2013
    Copy the full SHA
    eff7882 View commit details
  2. Mixxeo support

    Sebastien Bourdeauducq committed Jul 4, 2013
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    4cd360e View commit details
Showing with 139 additions and 136 deletions.
  1. +0 −21 Makefile
  2. +11 −16 README
  3. +0 −77 build.py
  4. +14 −0 jtag.py
  5. +0 −3 load.jtag
  6. +67 −0 make.py
  7. +13 −5 milkymist/dvisampler/__init__.py
  8. +11 −1 milkymist/dvisampler/clocking.py
  9. +2 −2 milkymist/{m1crg → mxcrg}/__init__.py
  10. +16 −10 top.py
  11. +5 −1 verilog/{m1crg/m1crg.v → mxcrg/mxcrg.v}
21 changes: 0 additions & 21 deletions Makefile

This file was deleted.

27 changes: 11 additions & 16 deletions README
Original file line number Diff line number Diff line change
@@ -2,17 +2,16 @@
------------------------------

This is the next-generation Milkymist(tm) system-on-chip design,
introducing two key innovations:
introducing two key features:
* Built on the powerful Migen VLSI logic design system.
* Increased system memory performance thanks to a new architecture
(ASMI) containing a transaction-reordering and superscalar controller.
* Increased system memory performance thanks to LASMI.

The Milkymist-NG SoC supports the Milkymist One board. Obtain yours at:
http://milkymist.org
This translates to more development productivity, better video resolution
and quality, ease of designing complex hardware accelerators, and much
more flexibility in hardware designs.

Note that the -NG version is still experimental work in progress. For the
production version of Milkymist SoC, visit:
https://github.com/milkymist/milkymist
The Milkymist-NG SoC supports the Mixxeo and the Milkymist One.
Obtain yours at http://milkymist.org

[> Instructions (software)
--------------------------
@@ -50,15 +49,11 @@ First, download and install Migen from:
https://github.com/milkymist/migen

Once this is done, build the bitstream with:
make
This will generate the build/soc.bit programming file.
Use:
make load
to load it with UrJTAG.
./make.py [-p <platform>] -l
This will generate the build/soc-<platform>.bit programming file
and load it with UrJTAG.

The SoC expects a bootloader to be located in flash at 0x860000, just
like the legacy SoC did. However, there is no binary compatibility and a
new BIOS needs to be built and flashed for the -NG SoC.
A new BIOS needs to be built and flashed for the -NG SoC.

Enjoy!

77 changes: 0 additions & 77 deletions build.py

This file was deleted.

14 changes: 14 additions & 0 deletions jtag.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,14 @@
import subprocess

def load(bitstream):
cmds = """cable milkymist
detect
pld load {bitstream}
quit
""".format(bitstream=bitstream)
process = subprocess.Popen("jtag", stdin=subprocess.PIPE)
process.stdin.write(cmds.encode("ASCII"))
process.communicate()

def flash(bitstream):
subprocess.call(["m1nor-ng", bitstream])
3 changes: 0 additions & 3 deletions load.jtag

This file was deleted.

67 changes: 67 additions & 0 deletions make.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,67 @@
#!/usr/bin/env python3

import argparse, os, importlib, subprocess

from mibuild.tools import write_to_file

from milkymist import cif
import top, jtag

def build(platform_name, build_bitstream, build_header):
platform_module = importlib.import_module("mibuild.platforms."+platform_name)
platform = platform_module.Platform()
soc = top.SoC(platform, platform_name)

platform.add_platform_command("""
INST "mxcrg/wr_bufpll" LOC = "BUFPLL_X0Y2";
INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3";
PIN "mxcrg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
""")

if hasattr(soc, "fb"):
platform.add_platform_command("""
NET "vga_clk" TNM_NET = "GRPvga_clk";
NET "sys_clk" TNM_NET = "GRPsys_clk";
TIMESPEC "TSise_sucks1" = FROM "GRPvga_clk" TO "GRPsys_clk" TIG;
TIMESPEC "TSise_sucks2" = FROM "GRPsys_clk" TO "GRPvga_clk" TIG;
""")

for d in ["mxcrg", "s6ddrphy", "minimac3"]:
platform.add_source_dir(os.path.join("verilog", d))
platform.add_sources(os.path.join("verilog", "lm32", "submodule", "rtl"),
"lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
"lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
"lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
"lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
"lm32_dcache.v", "lm32_top.v", "lm32_debug.v", "lm32_jtag.v", "jtag_cores.v",
"jtag_tap_spartan6.v", "lm32_itlb.v", "lm32_dtlb.v")
platform.add_sources(os.path.join("verilog", "lm32"), "lm32_config.v")

if build_bitstream:
build_name = "soc-"+platform_name
platform.build(soc, build_name=build_name)
subprocess.call(["tools/byteswap", build_name+".bin", build_name+".fpg"])
else:
soc.finalize()
if build_header:
csr_header = cif.get_csr_header(soc.csr_base, soc.csrbankarray, soc.interrupt_map)
write_to_file("software/include/hw/csr.h", csr_header)

def main():
parser = argparse.ArgumentParser(description="milkymist-ng - a high performance SoC built on Migen technology.")
parser.add_argument("-p", "--platform", default="mixxeo", help="platform to build for")
parser.add_argument("-B", "--no-bitstream", default=False, action="store_true", help="do not build bitstream file")
parser.add_argument("-H", "--no-header", default=False, action="store_true", help="do not build C header file with CSR/IRQ defs")
parser.add_argument("-l", "--load", default=False, action="store_true", help="load bitstream to SRAM")
parser.add_argument("-f", "--flash", default=False, action="store_true", help="load bitstream to flash")
args = parser.parse_args()

build(args.platform, not args.no_bitstream, not args.no_header)
if args.load:
jtag.load("build/soc-"+args.platform+".bit")
if args.flash:
jtag.flash("build/soc-"+args.platform+".fpg")

if __name__ == "__main__":
main()
18 changes: 13 additions & 5 deletions milkymist/dvisampler/__init__.py
Original file line number Diff line number Diff line change
@@ -19,11 +19,19 @@ def __init__(self, pads, asmiport, n_dma_slots=2):
for datan in range(3):
name = "data" + str(datan)
invert = False
try:
s = getattr(pads, name)
except AttributeError:
s = getattr(pads, name + "_n")
invert = True
if hasattr(pads, name + "_p"):
s = Signal()
self.specials += Instance("IBUFDS",
Instance.Input("I", getattr(pads, name + "_p")),
Instance.Input("IB", getattr(pads, name + "_n")),
Instance.Output("O", s)
)
else:
try:
s = getattr(pads, name)
except AttributeError:
s = getattr(pads, name + "_n")
invert = True

cap = DataCapture(8, invert)
setattr(self.submodules, name + "_cap", cap)
12 changes: 11 additions & 1 deletion milkymist/dvisampler/clocking.py
Original file line number Diff line number Diff line change
@@ -16,6 +16,16 @@ def __init__(self, pads):

###

if hasattr(pads, "clk_p"):
clkin = Signal()
self.specials += Instance("IBUFDS",
Instance.Input("I", pads.clk_p),
Instance.Input("IB", pads.clk_n),
Instance.Output("O", clkin)
)
else:
clkin = pads.clk

clkfbout = Signal()
pll_locked = Signal()
pll_clk0 = Signal()
@@ -39,7 +49,7 @@ def __init__(self, pads):
Instance.Output("CLKOUT3", pll_clk3),
Instance.Output("LOCKED", pll_locked),
Instance.Input("CLKFBIN", clkfbout),
Instance.Input("CLKIN", pads.clk),
Instance.Input("CLKIN", clkin),
Instance.Input("RST", self._r_pll_reset.storage)
)

4 changes: 2 additions & 2 deletions milkymist/m1crg/__init__.py → milkymist/mxcrg/__init__.py
Original file line number Diff line number Diff line change
@@ -3,7 +3,7 @@
from migen.fhdl.std import *
from migen.bank.description import *

class M1CRG(Module, AutoCSR):
class MXCRG(Module, AutoCSR):
def __init__(self, pads, outfreq1x):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x_270 = ClockDomain()
@@ -32,7 +32,7 @@ def __init__(self, pads, outfreq1x):
vga_progdone = Signal()
vga_locked = Signal()

self.specials += Instance("m1crg",
self.specials += Instance("mxcrg",
Instance.Parameter("in_period", in_period),
Instance.Parameter("f_mult", ratio.numerator),
Instance.Parameter("f_div", ratio.denominator),
26 changes: 16 additions & 10 deletions top.py
Original file line number Diff line number Diff line change
@@ -6,8 +6,9 @@
from migen.bus import wishbone, csr, lasmibus, dfi
from migen.bus import wishbone2lasmi, wishbone2csr
from migen.bank import csrgen
from mibuild.generic_platform import ConstraintError

from milkymist import m1crg, lm32, norflash, uart, s6ddrphy, dfii, lasmicon, \
from milkymist import mxcrg, lm32, norflash, uart, s6ddrphy, dfii, lasmicon, \
identifier, timer, minimac3, framebuffer, dvisampler, \
counteradc, gpio
from milkymist.cif import get_macros
@@ -51,10 +52,14 @@ def ns(t, margin=True):
write_time=16
)

class M1ClockPads:
class MXClockPads:
def __init__(self, platform):
self.clk50 = platform.request("clk50")
self.trigger_reset = platform.request("user_btn", 1)
self.trigger_reset = 0
try:
self.trigger_reset = platform.request("user_btn", 1)
except ConstraintError:
pass
self.norflash_rst_n = platform.request("norflash_rst_n")
self.vga_clk = platform.request("vga_clock")
ddram_clock = platform.request("ddram_clock")
@@ -93,7 +98,7 @@ class SoC(Module):
"dvisampler1": 4,
}

def __init__(self, platform):
def __init__(self, platform, platform_name):
#
# LASMI
#
@@ -142,18 +147,19 @@ def __init__(self, platform):
#
# CSR
#
self.submodules.crg = m1crg.M1CRG(M1ClockPads(platform), clk_freq)
self.submodules.crg = mxcrg.MXCRG(MXClockPads(platform), clk_freq)
self.submodules.uart = uart.UART(platform.request("serial"), clk_freq, baud=115200)
self.submodules.identifier = identifier.Identifier(0x4D31, version, int(clk_freq))
self.submodules.timer0 = timer.Timer()
self.submodules.fb = framebuffer.MixFramebuffer(platform.request("vga"), lasmim_fb0, lasmim_fb1)
self.submodules.dvisampler0 = dvisampler.DVISampler(platform.request("dvi_in", 0), lasmim_dvi0)
self.submodules.dvisampler1 = dvisampler.DVISampler(platform.request("dvi_in", 1), lasmim_dvi1)
pots_pads = platform.request("dvi_pots")
self.submodules.pots = counteradc.CounterADC(pots_pads.charge,
[pots_pads.blackout, pots_pads.crossfade])
self.submodules.buttons = gpio.GPIOIn(Cat(platform.request("user_btn", 0), platform.request("user_btn", 2)))
self.submodules.leds = gpio.GPIOOut(Cat(*[platform.request("user_led", i) for i in range(2)]))
if platform_name == "m1":
pots_pads = platform.request("dvi_pots")
self.submodules.pots = counteradc.CounterADC(pots_pads.charge,
[pots_pads.blackout, pots_pads.crossfade])
self.submodules.buttons = gpio.GPIOIn(Cat(platform.request("user_btn", 0), platform.request("user_btn", 2)))
self.submodules.leds = gpio.GPIOOut(Cat(*[platform.request("user_led", i) for i in range(2)]))

self.submodules.csrbankarray = csrgen.BankArray(self,
lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override])
6 changes: 5 additions & 1 deletion verilog/m1crg/m1crg.v → verilog/mxcrg/mxcrg.v
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
module m1crg #(
module mxcrg #(
parameter in_period = 0.0,
parameter f_mult = 0,
parameter f_div = 0,
@@ -56,6 +56,8 @@ always @(posedge sys_clk) begin
sys_rst <= rst_debounce != 20'd0;
end

initial rst_debounce <= 20'hFFFFF;

/*
* We must release the Flash reset before the system reset
* because the Flash needs some time to come out of reset
@@ -74,6 +76,8 @@ always @(posedge sys_clk) begin
flash_rstcounter <= flash_rstcounter + 8'd1;
end

initial flash_rstcounter <= 8'd0;

assign norflash_rst_n = flash_rstcounter[7];

/*