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  • 3 commits
  • 20 files changed
  • 1 contributor

Commits on Apr 10, 2013

  1. flow: use Module and new Record APIs

    Sebastien Bourdeauducq committed Apr 10, 2013
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    692794a View commit details
  2. genlib/record/connect: add match_by_position

    Sebastien Bourdeauducq committed Apr 10, 2013
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    df1ed32 View commit details
  3. flow: match record fields by position

    Sebastien Bourdeauducq committed Apr 10, 2013
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    6ce8562 View commit details
134 changes: 74 additions & 60 deletions examples/dataflow/dma.py
Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
from random import Random

from migen.fhdl.module import Module
from migen.flow.network import *
from migen.flow.transactions import *
from migen.actorlib import dma_wishbone, dma_asmi
@@ -26,88 +27,101 @@ def adrgen_gen():
print("Address: " + str(i))
yield Token("address", {"a": i})

class SimAdrGen(SimActor):
def __init__(self, nbits):
self.address = Source([("a", nbits)])
SimActor.__init__(self, adrgen_gen())

def dumper_gen():
while True:
t = Token("data", idle_wait=True)
yield t
print("Received: " + str(t.value["d"]))

class SimDumper(SimActor):
def __init__(self):
self.data = Sink([("d", 32)])
SimActor.__init__(self, dumper_gen())

def trgen_gen():
for i in range(10):
a = i
d = i+10
print("Address: " + str(a) + " Data: " + str(d))
yield Token("address_data", {"a": a, "d": d})

def wishbone_sim(efragment, master, end_simulation):
peripheral = wishbone.Target(MyModelWB())
tap = wishbone.Tap(peripheral.bus)
interconnect = wishbone.InterconnectPointToPoint(master.bus, peripheral.bus)
def _end_simulation(s):
s.interrupt = end_simulation(s)
fragment = efragment \
+ peripheral.get_fragment() \
+ tap.get_fragment() \
+ interconnect.get_fragment() \
+ Fragment(sim=[_end_simulation])
sim = Simulator(fragment)
sim.run()

def asmi_sim(efragment, hub, end_simulation):
def _end_simulation(s):
s.interrupt = end_simulation(s)
peripheral = asmibus.Target(MyModelASMI(), hub)
tap = asmibus.Tap(hub)
def _end_simulation(s):
s.interrupt = end_simulation(s)
fragment = efragment \
+ peripheral.get_fragment() \
+ tap.get_fragment() \
+ Fragment(sim=[_end_simulation])
sim = Simulator(fragment)
sim.run()
class SimTrGen(SimActor):
def __init__(self):
self.address_data = Source([("a", 30), ("d", 32)])
SimActor.__init__(self, trgen_gen())

class TBWishbone(Module):
def __init__(self, master):
self.submodules.peripheral = wishbone.Target(MyModelWB())
self.submodules.tap = wishbone.Tap(self.peripheral.bus)
self.submodules.interconnect = wishbone.InterconnectPointToPoint(master.bus,
self.peripheral.bus)

class TBWishboneReader(TBWishbone):
def __init__(self):
self.adrgen = SimAdrGen(30)
self.reader = dma_wishbone.Reader()
self.dumper = SimDumper()
g = DataFlowGraph()
g.add_connection(self.adrgen, self.reader)
g.add_connection(self.reader, self.dumper)
self.submodules.comp = CompositeActor(g)
TBWishbone.__init__(self, self.reader)

def do_simulation(self, s):
s.interrupt = self.adrgen.token_exchanger.done and not s.rd(self.comp.busy)

class TBWishboneWriter(TBWishbone):
def __init__(self):
self.trgen = SimTrGen()
self.writer = dma_wishbone.Writer()
g = DataFlowGraph()
g.add_connection(self.trgen, self.writer)
self.submodules.comp = CompositeActor(g)
TBWishbone.__init__(self, self.writer)

def do_simulation(self, s):
s.interrupt = self.trgen.token_exchanger.done and not s.rd(self.comp.busy)

class TBAsmi(Module):
def __init__(self, hub):
self.submodules.peripheral = asmibus.Target(MyModelASMI(), hub)
self.submodules.tap = asmibus.Tap(hub)

class TBAsmiReader(TBAsmi):
def __init__(self, nslots):
self.submodules.hub = asmibus.Hub(32, 32)
port = self.hub.get_port(nslots)
self.hub.finalize()

self.adrgen = SimAdrGen(32)
self.reader = dma_asmi.Reader(port)
self.dumper = SimDumper()
g = DataFlowGraph()
g.add_connection(self.adrgen, self.reader)
g.add_connection(self.reader, self.dumper)
self.submodules.comp = CompositeActor(g)
TBAsmi.__init__(self, self.hub)

def do_simulation(self, s):
s.interrupt = self.adrgen.token_exchanger.done and not s.rd(self.comp.busy)

def test_wb_reader():
print("*** Testing Wishbone reader")
adrgen = SimActor(adrgen_gen(), ("address", Source, [("a", 30)]))
reader = dma_wishbone.Reader()
dumper = SimActor(dumper_gen(), ("data", Sink, [("d", 32)]))
g = DataFlowGraph()
g.add_connection(adrgen, reader)
g.add_connection(reader, dumper)
comp = CompositeActor(g)

wishbone_sim(comp.get_fragment(), reader,
lambda s: adrgen.token_exchanger.done and not s.rd(comp.busy))
Simulator(TBWishboneReader()).run()

def test_wb_writer():
print("*** Testing Wishbone writer")
trgen = SimActor(trgen_gen(), ("address_data", Source, [("a", 30), ("d", 32)]))
writer = dma_wishbone.Writer()
g = DataFlowGraph()
g.add_connection(trgen, writer)
comp = CompositeActor(g)

wishbone_sim(comp.get_fragment(), writer,
lambda s: trgen.token_exchanger.done and not s.rd(comp.busy))
Simulator(TBWishboneWriter()).run()

def test_asmi_reader(nslots):
print("*** Testing ASMI reader (nslots={})".format(nslots))

hub = asmibus.Hub(32, 32)
port = hub.get_port(nslots)
hub.finalize()

adrgen = SimActor(adrgen_gen(), ("address", Source, [("a", 32)]))
reader = dma_asmi.Reader(port)
dumper = SimActor(dumper_gen(), ("data", Sink, [("d", 32)]))
g = DataFlowGraph()
g.add_connection(adrgen, reader)
g.add_connection(reader, dumper)
comp = CompositeActor(g)

asmi_sim(hub.get_fragment() + comp.get_fragment(), hub,
lambda s: adrgen.token_exchanger.done and not s.rd(comp.busy))
Simulator(TBAsmiReader(nslots)).run()

test_wb_reader()
test_wb_writer()
19 changes: 14 additions & 5 deletions examples/dataflow/misc.py
Original file line number Diff line number Diff line change
@@ -8,24 +8,33 @@ def source_gen():
for i in range(10):
v = i + 5
print("==> " + str(v))
yield Token("source", {"value": v})
yield Token("source", {"maximum": v})

class SimSource(SimActor):
def __init__(self):
self.source = Source([("maximum", 32)])
SimActor.__init__(self, source_gen())

def sink_gen():
while True:
t = Token("sink")
yield t
print(t.value["value"])

class SimSink(SimActor):
def __init__(self):
self.sink = Sink([("value", 32)])
SimActor.__init__(self, sink_gen())

def main():
source = SimActor(source_gen(), ("source", Source, [("value", 32)]))
source = SimSource()
loop = misc.IntSequence(32)
sink = SimActor(sink_gen(), ("sink", Sink, [("value", 32)]))
sink = SimSink()
g = DataFlowGraph()
g.add_connection(source, loop)
g.add_connection(loop, sink)
comp = CompositeActor(g)
fragment = comp.get_fragment()
sim = Simulator(fragment)
sim = Simulator(comp)
sim.run(500)

main()
67 changes: 38 additions & 29 deletions examples/dataflow/structuring.py
Original file line number Diff line number Diff line change
@@ -11,48 +11,57 @@
from migen.flow import perftools

pack_factor = 5
base_layout = [("value", 32)]
packed_layout = structuring.pack_layout(base_layout, pack_factor)
rawbits_layout = [("value", 32*pack_factor)]

def source_gen():
for i in count(0):
yield Token("source", {"value": i})

class SimSource(SimActor):
def __init__(self):
self.source = Source(base_layout)
SimActor.__init__(self, source_gen())

def sink_gen():
while True:
t = Token("sink")
yield t
print(t.value["value"])

class SimSink(SimActor):
def __init__(self):
self.sink = Sink(base_layout)
SimActor.__init__(self, sink_gen())

class TB(Module):
def __init__(self):
source = SimSource()
sink = SimSink()

# A tortuous way of passing integer tokens.
packer = structuring.Pack(base_layout, pack_factor)
to_raw = structuring.Cast(packed_layout, rawbits_layout)
from_raw = structuring.Cast(rawbits_layout, packed_layout)
unpacker = structuring.Unpack(pack_factor, base_layout)

self.g = DataFlowGraph()
self.g.add_connection(source, packer)
self.g.add_connection(packer, to_raw)
self.g.add_connection(to_raw, from_raw)
self.g.add_connection(from_raw, unpacker)
self.g.add_connection(unpacker, sink)
self.submodules.comp = CompositeActor(self.g)
self.submodules.reporter = perftools.DFGReporter(self.g)

def main():
base_layout = [("value", 32)]
packed_layout = structuring.pack_layout(base_layout, pack_factor)
rawbits_layout = [("value", 32*pack_factor)]

source = SimActor(source_gen(), ("source", Source, base_layout))
sink = SimActor(sink_gen(), ("sink", Sink, base_layout))
tb = TB()
sim = Simulator(tb).run(1000)

# A tortuous way of passing integer tokens.
packer = structuring.Pack(base_layout, pack_factor)
to_raw = structuring.Cast(packed_layout, rawbits_layout)
from_raw = structuring.Cast(rawbits_layout, packed_layout)
unpacker = structuring.Unpack(pack_factor, base_layout)

g = DataFlowGraph()
g.add_connection(source, packer)
g.add_connection(packer, to_raw)
g.add_connection(to_raw, from_raw)
g.add_connection(from_raw, unpacker)
g.add_connection(unpacker, sink)
comp = CompositeActor(g)
reporter = perftools.DFGReporter(g)

fragment = comp.get_fragment() + reporter.get_fragment()
sim = Simulator(fragment)
sim.run(1000)

g_layout = nx.spectral_layout(g)
nx.draw(g, g_layout)
nx.draw_networkx_edge_labels(g, g_layout, reporter.get_edge_labels())
g_layout = nx.spectral_layout(tb.g)
nx.draw(tb.g, g_layout)
nx.draw_networkx_edge_labels(tb.g, g_layout, tb.reporter.get_edge_labels())
plt.show()


main()
8 changes: 7 additions & 1 deletion examples/pytholite/basic.py
Original file line number Diff line number Diff line change
@@ -11,6 +11,11 @@ def number_gen():
for i in range(10):
yield Token("result", {"r": i})

class SimNumberGen(SimActor):
def __init__(self):
self.result = Source(layout)
SimActor.__init__(self, number_gen())

def run_sim(ng):
g = DataFlowGraph()
d = Dumper(layout)
@@ -23,14 +28,15 @@ def run_sim(ng):

def main():
print("Simulating native Python:")
ng_native = SimActor(number_gen(), ("result", Source, layout))
ng_native = SimNumberGen()
run_sim(ng_native)

print("Simulating Pytholite:")
ng_pytholite = make_pytholite(number_gen, dataflow=[("result", Source, layout)])
run_sim(ng_pytholite)

print("Converting Pytholite to Verilog:")
ng_pytholite = make_pytholite(number_gen, dataflow=[("result", Source, layout)])
print(verilog.convert(ng_pytholite))

main()
3 changes: 3 additions & 0 deletions examples/pytholite/uio.py
Original file line number Diff line number Diff line change
@@ -66,6 +66,9 @@ def main():
run_sim(ng_pytholite)

print("Converting Pytholite to Verilog:")
ng_pytholite = make_pytholite(gen,
dataflow=dataflow,
buses=buses)
print(verilog.convert(ng_pytholite.get_fragment()))

main()
33 changes: 21 additions & 12 deletions examples/sim/dataflow.py
Original file line number Diff line number Diff line change
@@ -10,22 +10,31 @@ def source_gen():
print("Sending: " + str(i))
yield Token("source", {"value": i})

class SimSource(SimActor):
def __init__(self):
self.source = Source([("value", 32)])
SimActor.__init__(self, source_gen())

def sink_gen():
while True:
t = Token("sink")
yield t
print("Received: " + str(t.value["value"]))

def main():
source = SimActor(source_gen(), ("source", Source, [("value", 32)]))
sink = SimActor(sink_gen(), ("sink", Sink, [("value", 32)]))
g = DataFlowGraph()
g.add_connection(source, sink)
comp = CompositeActor(g)
def end_simulation(s):
s.interrupt = source.token_exchanger.done
fragment = comp.get_fragment() + Fragment(sim=[end_simulation])
sim = Simulator(fragment)
sim.run()
class SimSink(SimActor):
def __init__(self):
self.sink = Sink([("value", 32)])
SimActor.__init__(self, sink_gen())

class TB(Module):
def __init__(self):
self.source = SimSource()
self.sink = SimSink()
g = DataFlowGraph()
g.add_connection(self.source, self.sink)
self.submodules.comp = CompositeActor(g)

def do_simulation(self, s):
s.interrupt = self.source.token_exchanger.done

main()
Simulator(TB()).run()
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