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base repository: m-labs/artiq
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  • 4 commits
  • 12 files changed
  • 1 contributor

Commits on Aug 13, 2014

  1. sim: use MPO

    sbourdeauducq committed Aug 13, 2014
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  4. MPO -> AutoContext

    sbourdeauducq committed Aug 13, 2014
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2 changes: 1 addition & 1 deletion artiq/devices/dds_core.py
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
from artiq.language.core import *
from artiq.language.units import *

class DDS(MPO):
class DDS(AutoContext):
parameters = "dds_sysclk reg_channel rtio_channel"

def build(self):
2 changes: 1 addition & 1 deletion artiq/devices/gpio_core.py
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
from artiq.language.core import *

class GPIOOut(MPO):
class GPIOOut(AutoContext):
parameters = "channel"

@kernel
2 changes: 1 addition & 1 deletion artiq/devices/ttl_core.py
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
from artiq.language.core import *

class TTLOut(MPO):
class TTLOut(AutoContext):
parameters = "channel"

@kernel
2 changes: 1 addition & 1 deletion artiq/language/core.py
Original file line number Diff line number Diff line change
@@ -5,7 +5,7 @@
def _make_kernel_ro(value):
return isinstance(value, (int, float, str, units.Quantity))

class MPO:
class AutoContext:
parameters = ""
implicit_core = True

34 changes: 15 additions & 19 deletions artiq/sim/devices.py
Original file line number Diff line number Diff line change
@@ -1,43 +1,39 @@
from random import Random

from artiq.language.core import AutoContext, delay
from artiq.language import units
from artiq.sim import time

class Core:
def run(self, k_function, k_args, k_kwargs):
return k_function(*k_args, **k_kwargs)

class Input:
def __init__(self, name, prng_seed=None, wait_max=20, count_max=100, wait_min=0, count_min=0):
self.name = name
self.wait_min = wait_min
self.wait_max = wait_max
self.count_min = count_min
self.count_max = count_max
self.prng = Random(prng_seed)
class Input(AutoContext):
parameters = "name"

def build(self):
self.prng = Random()

def wait_edge(self):
duration = self.prng.randrange(self.wait_min, self.wait_max)*units.ms
duration = self.prng.randrange(0, 20)*units.ms
time.manager.event(("wait_edge", self.name, duration))
time.manager.take_time(duration)
delay(duration)

def count_gate(self, duration):
result = self.prng.randrange(self.count_min, self.count_max)
result = self.prng.randrange(0, 100)
time.manager.event(("count_gate", self.name, duration, result))
time.manager.take_time(duration)
delay(duration)
return result

class WaveOutput:
def __init__(self, name):
self.name = name
class WaveOutput(AutoContext):
parameters = "name"

def pulse(self, frequency, duration):
time.manager.event(("pulse", self.name, frequency, duration))
time.manager.take_time(duration)
delay(duration)

class VoltageOutput:
def __init__(self, name):
self.name = name
class VoltageOutput(AutoContext):
parameters = "name"

def set(self, value):
time.manager.event(("set_voltage", self.name, value))
6 changes: 3 additions & 3 deletions doc/slides/artiq_overview.tex
Original file line number Diff line number Diff line change
@@ -86,7 +86,7 @@
\begin{frame}[fragile]
\frametitle{\fontseries{l}\selectfont Object orientation and code reuse}
\begin{verbatimtab}
class Main(MPO):
class Main(AutoContext):
def build(self):
self.ion1 = Ion(...)
self.ion2 = Ion(...)
@@ -130,9 +130,9 @@
\begin{frame}[fragile]
\frametitle{\fontseries{l}\selectfont Channels and parameters}
\begin{itemize}
\item A kernel is a method of a class that derives from the \verb!MPO! class
\item A kernel is a method of a class that derives from the \verb!AutoContext! class
\item The entry point for an experiment is called \verb!run! --- may or may not be a kernel
\item The \verb!MPO! class manages channels and parameters, and sets them as attributes
\item The \verb!AutoContext! class manages channels and parameters, and sets them as attributes
\item If channels/parameters are passed as constructor arguments, those are used
\item Otherwise, they are looked up in the device and parameter databases
\end{itemize}
2 changes: 1 addition & 1 deletion examples/al_spectroscopy.py
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
from artiq.language.units import *
from artiq.language.core import *

class AluminumSpectroscopy(MPO):
class AluminumSpectroscopy(AutoContext):
parameters = "mains_sync laser_cooling spectroscopy spectroscopy_b state_detection pmt \
spectroscopy_freq photon_limit_low photon_limit_high"

10 changes: 5 additions & 5 deletions examples/compiler_test.py
Original file line number Diff line number Diff line change
@@ -3,7 +3,7 @@

my_range = range

class CompilerTest(MPO):
class CompilerTest(AutoContext):
parameters = "a b A B"

def print_done(self):
@@ -33,9 +33,9 @@ def run(self, n, t2):
coredev = core.Core(corecom_dummy.CoreCom())
exp = CompilerTest(
core=coredev,
a=dds_core.DDS(coredev, 0, 0),
b=dds_core.DDS(coredev, 1, 1),
A=dds_core.DDS(coredev, 2, 2),
B=dds_core.DDS(coredev, 3, 3)
a=dds_core.DDS(core=coredev, dds_sysclk=1*GHz, reg_channel=0, rtio_channel=0),
b=dds_core.DDS(core=coredev, dds_sysclk=1*GHz, reg_channel=1, rtio_channel=1),
A=dds_core.DDS(core=coredev, dds_sysclk=1*GHz, reg_channel=2, rtio_channel=2),
B=dds_core.DDS(core=coredev, dds_sysclk=1*GHz, reg_channel=3, rtio_channel=3)
)
exp.run(3, 100*us)
4 changes: 2 additions & 2 deletions examples/coredev_test.py
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
from artiq.language.core import MPO, kernel
from artiq.language.core import AutoContext, kernel
from artiq.devices import corecom_serial, core, gpio_core

class CompilerTest(MPO):
class CompilerTest(AutoContext):
parameters = "led"

def output(self, n):
10 changes: 5 additions & 5 deletions examples/dds_test.py
Original file line number Diff line number Diff line change
@@ -2,7 +2,7 @@
from artiq.language.core import *
from artiq.devices import corecom_serial, core, dds_core, gpio_core

class DDSTest(MPO):
class DDSTest(AutoContext):
parameters = "a b c d led"

@kernel
@@ -28,10 +28,10 @@ def run(self):
coredev = core.Core(com)
exp = DDSTest(
core=coredev,
a=dds_core.DDS(core=coredev, dds_sysclk=1000*MHz, reg_channel=0, rtio_channel=0),
b=dds_core.DDS(core=coredev, dds_sysclk=1000*MHz, reg_channel=1, rtio_channel=1),
c=dds_core.DDS(core=coredev, dds_sysclk=1000*MHz, reg_channel=2, rtio_channel=2),
d=dds_core.DDS(core=coredev, dds_sysclk=1000*MHz, reg_channel=3, rtio_channel=3),
a=dds_core.DDS(core=coredev, dds_sysclk=1*GHz, reg_channel=0, rtio_channel=0),
b=dds_core.DDS(core=coredev, dds_sysclk=1*GHz, reg_channel=1, rtio_channel=1),
c=dds_core.DDS(core=coredev, dds_sysclk=1*GHz, reg_channel=2, rtio_channel=2),
d=dds_core.DDS(core=coredev, dds_sysclk=1*GHz, reg_channel=3, rtio_channel=3),
led=gpio_core.GPIOOut(core=coredev, channel=1)
)
exp.run()
13 changes: 7 additions & 6 deletions examples/simple_simulation.py
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
from artiq.language.units import *
from artiq.language.core import *

class SimpleSimulation(MPO):
class SimpleSimulation(AutoContext):
parameters = "a b c d"

@kernel
@@ -18,12 +18,13 @@ def run(self):
from artiq.sim import devices as sd
from artiq.sim import time

coredev = sd.Core()
exp = SimpleSimulation(
core=sd.Core(),
a=sd.WaveOutput("a"),
b=sd.WaveOutput("b"),
c=sd.WaveOutput("c"),
d=sd.WaveOutput("d"),
core=coredev,
a=sd.WaveOutput(core=coredev, name="a"),
b=sd.WaveOutput(core=coredev, name="b"),
c=sd.WaveOutput(core=coredev, name="c"),
d=sd.WaveOutput(core=coredev, name="d"),
)
exp.run()
print(time.manager.format_timeline())
4 changes: 2 additions & 2 deletions examples/time_test.py
Original file line number Diff line number Diff line change
@@ -2,7 +2,7 @@
from artiq.language.core import *
from artiq.devices import corecom_serial, core

class DummyPulse(MPO):
class DummyPulse(AutoContext):
parameters = "name"

def print_on(self, t, f):
@@ -17,7 +17,7 @@ def pulse(self, f, duration):
delay(duration)
self.print_off(now())

class TimeTest(MPO):
class TimeTest(AutoContext):
parameters = "a b c d"

@kernel