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Commit 738b45d

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author
Sebastien Bourdeauducq
committedDec 16, 2011
Support the new FHDL syntax
1 parent ca68097 commit 738b45d

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4 files changed

+33
-34
lines changed

4 files changed

+33
-34
lines changed
 

‎milkymist/lm32/__init__.py

+11-11
Original file line numberDiff line numberDiff line change
@@ -1,21 +1,21 @@
1-
from migen.fhdl import structure as f
1+
from migen.fhdl.structure import *
22
from migen.bus import wishbone
33

44
class Inst:
55
def __init__(self):
66
self.ibus = i = wishbone.Master("lm32i")
77
self.dbus = d = wishbone.Master("lm32d")
8-
f.declare_signal(self, "interrupt", f.BV(32))
9-
f.declare_signal(self, "ext_break")
10-
self._inst = f.Instance("lm32_top",
8+
declare_signal(self, "interrupt", BV(32))
9+
declare_signal(self, "ext_break")
10+
self._inst = Instance("lm32_top",
1111
[("I_ADR_O", i.adr_o),
1212
("I_DAT_O", i.dat_o),
1313
("I_SEL_O", i.sel_o),
1414
("I_CYC_O", i.cyc_o),
1515
("I_STB_O", i.stb_o),
1616
("I_WE_O", i.we_o),
1717
("I_CTI_O", i.cti_o),
18-
("I_LOCK_O", f.BV(1)),
18+
("I_LOCK_O", BV(1)),
1919
("I_BTE_O", i.bte_o),
2020
("D_ADR_O", d.adr_o),
2121
("D_DAT_O", d.dat_o),
@@ -24,26 +24,26 @@ def __init__(self):
2424
("D_STB_O", d.stb_o),
2525
("D_WE_O", d.we_o),
2626
("D_CTI_O", d.cti_o),
27-
("D_LOCK_O", f.BV(1)),
27+
("D_LOCK_O", BV(1)),
2828
("D_BTE_O", d.bte_o)],
2929
[("interrupt", self.interrupt),
3030
#("ext_break", self.ext_break),
3131
("I_DAT_I", i.dat_i),
3232
("I_ACK_I", i.ack_i),
3333
("I_ERR_I", i.err_i),
34-
("I_RTY_I", f.BV(1)),
34+
("I_RTY_I", BV(1)),
3535
("D_DAT_I", d.dat_i),
3636
("D_ACK_I", d.ack_i),
3737
("D_ERR_I", d.err_i),
38-
("D_RTY_I", f.BV(1))],
38+
("D_RTY_I", BV(1))],
3939
[],
4040
"clk_i",
4141
"rst_i",
4242
"lm32")
4343

4444
def get_fragment(self):
4545
comb = [
46-
f.Assign(self._inst.ins["I_RTY_I"], 0),
47-
f.Assign(self._inst.ins["D_RTY_I"], 0)
46+
self._inst.ins["I_RTY_I"].eq(0),
47+
self._inst.ins["D_RTY_I"].eq(0)
4848
]
49-
return f.Fragment(comb=comb, instances=[self._inst])
49+
return Fragment(comb=comb, instances=[self._inst])

‎milkymist/norflash/__init__.py

+13-13
Original file line numberDiff line numberDiff line change
@@ -1,32 +1,32 @@
11
from functools import partial
22

3-
from migen.fhdl import structure as f
3+
from migen.fhdl.structure import *
44
from migen.bus import wishbone
55
from migen.corelogic import timeline
66

77
class Inst:
88
def __init__(self, adr_width, rd_timing):
99
self.bus = wishbone.Slave("norflash")
10-
d = partial(f.declare_signal, self)
11-
d("adr", f.BV(adr_width-1))
12-
d("d", f.BV(16))
10+
d = partial(declare_signal, self)
11+
d("adr", BV(adr_width-1))
12+
d("d", BV(16))
1313
d("oe_n")
1414
d("we_n")
1515
d("ce_n")
1616
d("rst_n")
1717
self.timeline = timeline.Inst(self.bus.cyc_i & self.bus.stb_i,
18-
[(0, [f.Assign(self.adr, f.Cat(0, self.bus.adr_i[2:adr_width]))]),
18+
[(0, [self.adr.eq(Cat(0, self.bus.adr_i[2:adr_width]))]),
1919
(rd_timing, [
20-
f.Assign(self.bus.dat_o[16:], self.d),
21-
f.Assign(self.adr, f.Cat(1, self.bus.adr_i[2:adr_width]))]),
20+
self.bus.dat_o[16:].eq(self.d),
21+
self.adr.eq(Cat(1, self.bus.adr_i[2:adr_width]))]),
2222
(2*rd_timing, [
23-
f.Assign(self.bus.dat_o[:16], self.d),
24-
f.Assign(self.bus.ack_o, 1)]),
23+
self.bus.dat_o[:16].eq(self.d),
24+
self.bus.ack_o.eq(1)]),
2525
(2*rd_timing+1, [
26-
f.Assign(self.bus.ack_o, 0)])])
26+
self.bus.ack_o.eq(0)])])
2727

2828
def get_fragment(self):
29-
comb = [f.Assign(self.oe_n, 0), f.Assign(self.we_n, 1),
30-
f.Assign(self.ce_n, 0), f.Assign(self.rst_n, 1)]
31-
return f.Fragment(comb, pads={self.adr, self.d, self.oe_n, self.we_n, self.ce_n, self.rst_n}) \
29+
comb = [self.oe_n.eq(0), self.we_n.eq(1),
30+
self.ce_n.eq(0), self.rst_n.eq(1)]
31+
return Fragment(comb, pads={self.adr, self.d, self.oe_n, self.we_n, self.ce_n, self.rst_n}) \
3232
+ self.timeline.get_fragment()

‎milkymist/uart/__init__.py

+9-9
Original file line numberDiff line numberDiff line change
@@ -1,14 +1,14 @@
1-
from migen.fhdl import structure as f
1+
from migen.fhdl.structure import *
22
from migen.bus import csr
33

44
class Inst:
5-
def __init__(self, csr_addr, clk_freq, baud=115200, break_en_default=f.Constant(0)):
5+
def __init__(self, csr_addr, clk_freq, baud=115200, break_en_default=Constant(0)):
66
self.bus = csr.Slave("uart")
7-
f.declare_signal(self, "tx")
8-
f.declare_signal(self, "rx")
9-
f.declare_signal(self, "irq")
10-
f.declare_signal(self, "brk")
11-
self._inst = f.Instance("uart",
7+
declare_signal(self, "tx")
8+
declare_signal(self, "rx")
9+
declare_signal(self, "irq")
10+
declare_signal(self, "brk")
11+
self._inst = Instance("uart",
1212
[("csr_do", self.bus.d_o),
1313
("uart_tx", self.tx),
1414
("irq", self.irq),
@@ -17,12 +17,12 @@ def __init__(self, csr_addr, clk_freq, baud=115200, break_en_default=f.Constant(
1717
("csr_we", self.bus.we_i),
1818
("csr_di", self.bus.d_i),
1919
("uart_rx", self.rx)],
20-
[("csr_addr", f.Constant(csr_addr, f.BV(4))),
20+
[("csr_addr", Constant(csr_addr, BV(4))),
2121
("clk_freq", clk_freq),
2222
("baud", baud),
2323
("break_en_default", break_en_default)],
2424
"sys_clk",
2525
"sys_rst")
2626

2727
def get_fragment(self):
28-
return f.Fragment(instances=[self._inst], pads={self.tx, self.rx})
28+
return Fragment(instances=[self._inst], pads={self.tx, self.rx})

‎tb/norflash/norflash_conv.py

-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,4 @@
11
from migen.fhdl import verilog
2-
from migen.fhdl import structure as f
32
from migen.bus import wishbone
43
from milkymist import norflash
54

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