@@ -24,7 +24,7 @@ def write(self, data):
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written = self .dev .write (data )
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if written < 0 :
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raise pylibftdi .FtdiError (written ,
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- self .dev .get_error_string ())
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+ self .dev .get_error_string ())
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return written
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def close (self ):
@@ -82,31 +82,31 @@ class Pdq2:
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"""
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PDQ DAC (a.k.a. QC_Waveform)
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"""
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- max_val = 1 << 15 # signed 16 bit DAC
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+ max_val = 1 << 15 # signed 16 bit DAC
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max_out = 10.
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- freq = 50e6 # samples/s
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- max_time = 1 << 16 # unsigned 16 bit timer
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+ freq = 50e6 # samples/s
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+ max_time = 1 << 16 # unsigned 16 bit timer
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num_dacs = 3
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num_frames = 8
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num_channels = 9
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- max_data = 4 * (1 << 10 ) # 8kx16 8kx16 4kx16
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+ max_data = 4 * (1 << 10 ) # 8kx16 8kx16 4kx16
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escape_char = b"\xa5 "
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cordic_gain = 1.
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for i in range (16 ):
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cordic_gain *= np .sqrt (1 + 2 ** (- 2 * i ))
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commands = {
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- "RESET_EN" : b"\x00 " ,
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- "RESET_DIS" : b"\x01 " ,
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- "TRIGGER_EN" : b"\x02 " ,
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- "TRIGGER_DIS" : b"\x03 " ,
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- "ARM_EN" : b"\x04 " ,
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- "ARM_DIS" : b"\x05 " ,
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- "DCM_EN" : b"\x06 " ,
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- "DCM_DIS" : b"\x07 " ,
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- "START_EN" : b"\x08 " ,
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- "START_DIS" : b"\x09 " ,
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- }
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+ "RESET_EN" : b"\x00 " ,
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+ "RESET_DIS" : b"\x01 " ,
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+ "TRIGGER_EN" : b"\x02 " ,
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+ "TRIGGER_DIS" : b"\x03 " ,
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+ "ARM_EN" : b"\x04 " ,
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+ "ARM_DIS" : b"\x05 " ,
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+ "DCM_EN" : b"\x06 " ,
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+ "DCM_DIS" : b"\x07 " ,
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+ "START_EN" : b"\x08 " ,
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+ "START_DIS" : b"\x09 " ,
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+ }
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def __init__ (self , serial = None ):
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self .serial = serial
@@ -123,8 +123,8 @@ def write_cmd(self, cmd):
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return self .write (self .cmd (cmd ))
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def escape (self , data ):
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- return data .replace (self .escape_char , self . escape_char +
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- self .escape_char )
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+ return data .replace (self .escape_char ,
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+ self . escape_char + self .escape_char )
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def write (self , * segments ):
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"""
@@ -158,13 +158,13 @@ def interpolate(self, t, v, order, shift=0, tr=None):
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if tr is None :
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tr = t
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dv = [interpolate .splev (tr [:- 1 ], spline , der = i )
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- for i in range (order + 1 )]
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+ for i in range (order + 1 )]
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# correct for adder chain latency
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correction_map = [
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- (1 , - 1 / 2. , 2 ),
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- (1 , - 1 / 6. , 3 ),
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- (2 , - 1. , 3 ),
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- ]
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+ (1 , - 1 / 2. , 2 ),
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+ (1 , - 1 / 6. , 3 ),
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+ (2 , - 1. , 3 ),
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+ ]
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for i , c , j in correction_map :
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if j >= len (dv ):
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break
@@ -180,14 +180,14 @@ def pack_frame(self, *parts_dtypes):
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frame .append ((part >> 32 ).astype ("<i2" ))
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else :
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frame .append (part .astype ("<" + dtype ))
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- frame = np .rec .fromarrays (frame ) # interleave
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+ frame = np .rec .fromarrays (frame ) # interleave
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logger .debug ("frame %s dtype %s shape %s length %s" ,
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- frame , frame .dtype , frame .shape , len (bytes (frame .data )))
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+ frame , frame .dtype , frame .shape , len (bytes (frame .data )))
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return bytes (frame .data )
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def frame (self , t , v , p = None , f = None ,
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- order = 3 , aux = None , shift = 0 , trigger = True , end = True ,
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- silence = False , stop = True , clear = True , wait = False ):
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+ order = 3 , aux = None , shift = 0 , trigger = True , end = True ,
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+ silence = False , stop = True , clear = True , wait = False ):
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"""
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serialize frame data
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voltages in volts, times in seconds
@@ -204,17 +204,17 @@ def frame(self, t, v, p=None, f=None,
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parts = []
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head = np .zeros (len (t ) - 1 , "<u2" )
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- head [:] |= length # 4
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+ head [:] |= length # 4
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if p is not None :
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- head [:] |= 1 << 4 # typ # 2
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- head [0 ] |= trigger << 6 # 1
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- head [- 1 ] |= (not stop and silence )<< 7 # 1
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+ head [:] |= 1 << 4 # typ # 2
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+ head [0 ] |= trigger << 6 # 1
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+ head [- 1 ] |= (not stop and silence ) << 7 # 1
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if aux is not None :
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- head [:] |= aux [:len (head )]<< 8 # 1
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- head [:] |= shift << 9 # 4
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- head [- 1 ] |= (not stop and end )<< 13 # 1
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- head [0 ] |= clear << 14 # 1
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- head [- 1 ] |= (not stop and wait )<< 15 # 1
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+ head [:] |= aux [:len (head )] << 8 # 1
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+ head [:] |= shift << 9 # 4
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+ head [- 1 ] |= (not stop and end ) << 13 # 1
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+ head [0 ] |= clear << 14 # 1
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+ head [- 1 ] |= (not stop and wait ) << 15 # 1
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parts .append ((head , "u2" ))
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t , tr , dt = self .line_times (t , shift )
@@ -243,19 +243,21 @@ def frame(self, t, v, p=None, f=None,
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if stop :
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if p is not None :
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- frame += struct .pack ("<HH hiihih H ii" , (15 << 0 ) | (1 << 4 ) |
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- (silence << 7 ) | (end << 13 ) | (wait << 15 ),
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- 1 , int (v [- 1 ]* 2 ** 15 ), 0 , 0 , 0 , 0 , 0 ,
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- int (p [- 1 ]* 2 ** 16 ), int (f [- 1 ]* 2 ** 31 ), 0 )
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+ frame += struct .pack ("<HH hiihih H ii" , (15 << 0 ) | (1 << 4 ) |
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+ (silence << 7 ) |
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+ (end << 13 ) |
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+ (wait << 15 ),
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+ 1 , int (v [- 1 ]* 2 ** 15 ), 0 , 0 , 0 , 0 , 0 ,
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+ int (p [- 1 ]* 2 ** 16 ), int (f [- 1 ]* 2 ** 31 ), 0 )
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else :
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- frame += struct .pack ("<HH h" , (2 << 0 ) |
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- ( silence << 7 ) | (end << 13 ) | (wait << 15 ),
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- 1 , int (v [- 1 ]* 2 ** 15 ))
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+ frame += struct .pack ("<HH h" , (2 << 0 ) | ( silence << 7 ) |
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+ (end << 13 ) | (wait << 15 ),
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+ 1 , int (v [- 1 ]* 2 ** 15 ))
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return frame
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def line (self , dt , v = (), a = (), p = (), f = (), typ = 0 ,
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- silence = False , end = False , trigger = False , aux = False ,
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- clear = False ):
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+ silence = False , end = False , trigger = False , aux = False ,
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+ clear = False ):
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raise NotImplementedError
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fmt = "<HH"
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parts = [0 , int (round (dt * self .freq ))]
@@ -292,7 +294,7 @@ def map_frames(self, frames, map=None):
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def add_mem_header (self , board , dac , data , adr = 0 ):
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assert dac in range (self .num_dacs )
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head = struct .pack ("<HHH" , (board << 4 ) | dac ,
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- adr , adr + len (data )// 2 - 1 )
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+ adr , adr + len (data )// 2 - 1 )
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return head + data
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def multi_frame (self , times_voltages , channel , map = None , ** kwargs ):
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