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base repository: m-labs/artiq
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base: 42accd5de442
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head repository: m-labs/artiq
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compare: 391ff10345e7
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  • 2 commits
  • 1 file changed
  • 2 contributors

Commits on Nov 7, 2014

  1. Copy the full SHA
    62677ed View commit details
  2. Copy the full SHA
    391ff10 View commit details
Showing with 8 additions and 0 deletions.
  1. +8 −0 test/full_stack.py
8 changes: 8 additions & 0 deletions test/full_stack.py
Original file line number Diff line number Diff line change
@@ -1,11 +1,15 @@
import unittest
from operator import itemgetter
import os

from artiq import *
from artiq.coredevice import comm_serial, core, runtime_exceptions, rtio
from artiq.sim import devices as sim_devices


no_hardware = bool(os.getenv("ARTIQ_NO_HARDWARE"))


def _run_on_device(k_class, **parameters):
with comm_serial.Comm() as comm:
coredev = core.Core(comm)
@@ -132,6 +136,7 @@ def run(self):
self.trace.append(104)


@unittest.skipIf(no_hardware, "no hardware")
class ExecutionCase(unittest.TestCase):
def test_primes(self):
l_device, l_host = [], []
@@ -203,7 +208,10 @@ def run(self):
self.o.pulse(25*us)


@unittest.skipIf(no_hardware, "no hardware")
class RTIOCase(unittest.TestCase):
# Connect channels 0 and 1 together for this test
# (C11 and C13 on Papilio Pro)
def test_loopback(self):
npulses = 4
with comm_serial.Comm() as comm: