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base repository: m-labs/migen
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head repository: m-labs/migen
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compare: 8adf6027e1c2
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  • 4 commits
  • 2 files changed
  • 1 contributor

Commits on Aug 3, 2014

  1. mibuild/programmer: fix XC3SProg init

    @sbourdeauducq
    sbourdeauducq committed Aug 3, 2014
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    536a220 View commit details

  2. platforms/kc705: use Vivado by default

    @sbourdeauducq
    sbourdeauducq committed Aug 3, 2014
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    210cb72 View commit details

  3. platforms/kc705: use XC3SProg

    @sbourdeauducq
    sbourdeauducq committed Aug 3, 2014
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    40dcc8b View commit details

  4. platforms/kc705: add automatic clk200 constraint

    @sbourdeauducq
    sbourdeauducq committed Aug 3, 2014
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    8adf602 View commit details
Showing with 10 additions and 2 deletions.
  1. +9 −1 mibuild/platforms/kc705.py
  2. +1 −1 mibuild/programmer.py
10 changes: 9 additions & 1 deletion mibuild/platforms/kc705.py
View file
Original file line number Diff line number Diff line change
@@ -3,6 +3,7 @@
from mibuild.xilinx_common import CRG_DS
from mibuild.xilinx_ise import XilinxISEPlatform
from mibuild.xilinx_vivado import XilinxVivadoPlatform
from mibuild.programmer import XC3SProg

_io = [
("user_led", 0, Pins("AB8"), IOStandard("LVCMOS15")),
@@ -117,7 +118,7 @@
),
]

def Platform(*args, toolchain="ise", **kwargs):
def Platform(*args, toolchain="vivado", **kwargs):
if toolchain == "ise":
xilinx_platform = XilinxISEPlatform
elif toolchain == "vivado":
@@ -129,9 +130,16 @@ class RealPlatform(xilinx_platform):
def __init__(self, crg_factory=lambda p: CRG_DS(p, "clk156", "cpu_reset")):
xilinx_platform.__init__(self, "xc7k325t-ffg900-1", _io, crg_factory)

def create_programmer(self):
return XC3SProg("jtaghs1", "bscan_spi_kc705.bit")

def do_finalize(self, fragment):
try:
self.add_period_constraint(self.lookup_request("clk156").p, 6.4)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("clk200").p, 5.0)
except ConstraintError:
pass
return RealPlatform(*args, **kwargs)
2 changes: 1 addition & 1 deletion mibuild/programmer.py
View file
Original file line number Diff line number Diff line change
@@ -53,7 +53,7 @@ class XC3SProg(Programmer):
needs_flash_proxy = True

def __init__(self, cable, flash_proxy_basename=None):
Programmer.__init__(flash_proxy_basename)
Programmer.__init__(self, flash_proxy_basename)
self.cable = cable

def load_bitstream(self, bitstream_file):