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Commit 1e860c7

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author
Sebastien Bourdeauducq
committedMar 26, 2013
Use new Mibuild generic_platform API
·
0.120.1
1 parent 1045d64 commit 1e860c7

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11 files changed

+137
-184
lines changed

11 files changed

+137
-184
lines changed
 

‎build.py

+12-30
Original file line numberDiff line numberDiff line change
@@ -9,27 +9,10 @@
99
import cif
1010

1111
def main():
12-
plat = m1.Platform()
13-
soc = top.SoC()
12+
platform = m1.Platform()
13+
soc = top.SoC(platform)
1414

15-
# set pin constraints
16-
plat.request("clk50", obj=soc.crg.clk50_pad)
17-
plat.request("user_btn", 1, obj=soc.crg.trigger_reset)
18-
plat.request("norflash_rst_n", obj=soc.crg.norflash_rst_n)
19-
plat.request("vga_clock", obj=soc.crg.vga_clk_pad)
20-
plat.request("ddram_clock", obj=soc.crg, name_map=lambda s: "ddr_clk_pad_" + s)
21-
plat.request("eth_clocks", obj=soc.crg, name_map=lambda s: "eth_" + s + "_clk_pad")
22-
23-
plat.request("norflash", obj=soc.norflash)
24-
plat.request("serial", obj=soc.uart)
25-
plat.request("ddram", obj=soc.ddrphy, name_map=lambda s: "sd_" + s)
26-
plat.request("eth", obj=soc.minimac, name_map=lambda s: "phy_" + s)
27-
plat.request("vga", obj=soc.fb, name_map=lambda s: "vga_" + s)
28-
plat.request("dvi_in", 0, obj=soc.dvisampler0)
29-
plat.request("dvi_in", 1, obj=soc.dvisampler1)
30-
31-
# set extra constraints
32-
plat.add_platform_command("""
15+
platform.add_platform_command("""
3316
NET "{clk50}" TNM_NET = "GRPclk50";
3417
TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%;
3518
INST "m1crg/wr_bufpll" LOC = "BUFPLL_X0Y2";
@@ -55,25 +38,24 @@ def main():
5538
NET "{dviclk1}" CLOCK_DEDICATED_ROUTE = FALSE;
5639
TIMESPEC "TSdviclk1" = PERIOD "GRPdviclk1" 26.7 ns HIGH 50%;
5740
""",
58-
clk50=soc.crg.clk50_pad,
59-
phy_rx_clk=soc.crg.eth_rx_clk_pad,
60-
phy_tx_clk=soc.crg.eth_tx_clk_pad,
61-
dviclk0=soc.dvisampler0.clk,
62-
dviclk1=soc.dvisampler1.clk)
41+
clk50=platform.lookup_request("clk50"),
42+
phy_rx_clk=platform.lookup_request("eth_clocks").rx,
43+
phy_tx_clk=platform.lookup_request("eth_clocks").tx,
44+
dviclk0=platform.lookup_request("dvi_in", 0).clk,
45+
dviclk1=platform.lookup_request("dvi_in", 1).clk)
6346

64-
# add Verilog sources
6547
for d in ["generic", "m1crg", "s6ddrphy", "minimac3"]:
66-
plat.add_source_dir(os.path.join("verilog", d))
67-
plat.add_sources(os.path.join("verilog", "lm32", "submodule", "rtl"),
48+
platform.add_source_dir(os.path.join("verilog", d))
49+
platform.add_sources(os.path.join("verilog", "lm32", "submodule", "rtl"),
6850
"lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
6951
"lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
7052
"lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
7153
"lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
7254
"lm32_dcache.v", "lm32_top.v", "lm32_debug.v", "lm32_jtag.v", "jtag_cores.v",
7355
"jtag_tap_spartan6.v", "lm32_itlb.v", "lm32_dtlb.v")
74-
plat.add_sources(os.path.join("verilog", "lm32"), "lm32_config.v")
56+
platform.add_sources(os.path.join("verilog", "lm32"), "lm32_config.v")
7557

76-
plat.build_cmdline(soc)
58+
platform.build_cmdline(soc)
7759
csr_header = cif.get_csr_header(soc.csr_base, soc.csrbankarray, soc.interrupt_map)
7860
write_to_file("software/include/hw/csr.h", csr_header)
7961

‎milkymist/dvisampler/__init__.py

+10-13
Original file line numberDiff line numberDiff line change
@@ -11,22 +11,19 @@
1111
from milkymist.dvisampler.resdetection import ResolutionDetection
1212

1313
class DVISampler(Module, AutoReg):
14-
def __init__(self, inversions=""):
15-
self.submodules.edid = EDID()
16-
self.sda = self.edid.sda
17-
self.scl = self.edid.scl
14+
def __init__(self, pads):
15+
self.submodules.edid = EDID(pads)
16+
self.submodules.clocking = Clocking(pads)
1817

19-
self.submodules.clocking = Clocking()
20-
self.clk = self.clocking.clkin
21-
22-
for datan in "012":
18+
for datan in range(3):
2319
name = "data" + str(datan)
24-
invert = datan in inversions
20+
invert = False
21+
try:
22+
s = getattr(pads, name)
23+
except AttributeError:
24+
s = getattr(pads, name + "_n")
25+
invert = True
2526

26-
signame = name + "_n" if invert else name
27-
s = Signal(name=signame)
28-
setattr(self, signame, s)
29-
3027
cap = DataCapture(8, invert)
3128
setattr(self.submodules, name + "_cap", cap)
3229
self.comb += [

‎milkymist/dvisampler/clocking.py

+2-4
Original file line numberDiff line numberDiff line change
@@ -5,9 +5,7 @@
55
from migen.bank.description import *
66

77
class Clocking(Module, AutoReg):
8-
def __init__(self):
9-
self.clkin = Signal()
10-
8+
def __init__(self, pads):
119
self._r_pll_reset = RegisterField()
1210
self._r_locked = RegisterField(1, READ_ONLY, WRITE_ONLY)
1311

@@ -43,7 +41,7 @@ def __init__(self):
4341
Instance.Output("CLKOUT3", pll_clk3),
4442
Instance.Output("LOCKED", pll_locked),
4543
Instance.Input("CLKFBIN", clkfbout),
46-
Instance.Input("CLKIN", self.clkin),
44+
Instance.Input("CLKIN", pads.clk),
4745
Instance.Input("RST", self._r_pll_reset.field.r)
4846
)
4947

‎milkymist/dvisampler/edid.py

+4-7
Original file line numberDiff line numberDiff line change
@@ -18,10 +18,7 @@
1818
]
1919

2020
class EDID(Module, AutoReg):
21-
def __init__(self, default=_default_edid):
22-
self.scl = Signal()
23-
self.sda = Signal()
24-
21+
def __init__(self, pads, default=_default_edid):
2522
self.specials.mem = Memory(8, 128, init=default)
2623

2724
###
@@ -33,9 +30,9 @@ def __init__(self, default=_default_edid):
3330
_sda_i_async = Signal()
3431
self.sync += _sda_drv_reg.eq(sda_drv)
3532
self.specials += [
36-
MultiReg(self.scl, scl_i, "sys"),
37-
Tristate(self.sda, 0, _sda_drv_reg, _sda_i_async),
38-
MultiReg(_sda_i_async, sda_i, "sys")
33+
MultiReg(pads.scl, scl_i),
34+
Tristate(pads.sda, 0, _sda_drv_reg, _sda_i_async),
35+
MultiReg(_sda_i_async, sda_i)
3936
]
4037

4138
# FIXME: understand what is really going on here and get rid of that workaround

‎milkymist/framebuffer/__init__.py

+10-17
Original file line numberDiff line numberDiff line change
@@ -161,7 +161,7 @@ def sim_fifo_gen():
161161
+ " " + str(t.value["r"]) + " " + str(t.value["g"]) + " " + str(t.value["b"]))
162162

163163
class Framebuffer(Module):
164-
def __init__(self, asmiport, simulation=False):
164+
def __init__(self, pads, asmiport, simulation=False):
165165
asmi_bits = asmiport.hub.aw
166166
alignment_bits = bits_for(asmiport.hub.dw//8) - 1
167167
length_bits = _hbits + _vbits + 2 - alignment_bits
@@ -197,23 +197,16 @@ def __init__(self, asmiport, simulation=False):
197197

198198
self._registers = fi.get_registers() + self._comp_actor.get_registers()
199199

200-
# Pads
201-
self.vga_psave_n = Signal()
200+
# Drive pads
202201
if not simulation:
203-
self.vga_hsync_n = fifo.vga_hsync_n
204-
self.vga_vsync_n = fifo.vga_vsync_n
205-
self.vga_sync_n = Signal()
206-
self.vga_blank_n = Signal()
207-
if not simulation:
208-
self.vga_r = fifo.vga_r
209-
self.vga_g = fifo.vga_g
210-
self.vga_b = fifo.vga_b
211-
212-
self.comb += [
213-
self.vga_sync_n.eq(0),
214-
self.vga_psave_n.eq(1),
215-
self.vga_blank_n.eq(1)
216-
]
202+
self.comb += [
203+
pads.hsync_n.eq(fifo.vga_hsync_n),
204+
pads.vsync_n.eq(fifo.vga_vsync_n),
205+
pads.r.eq(fifo.vga_r),
206+
pads.g.eq(fifo.vga_g),
207+
pads.b.eq(fifo.vga_b)
208+
]
209+
self.comb += pads.psave_n.eq(1)
217210

218211
def get_registers(self):
219212
return self._registers

‎milkymist/m1crg/__init__.py

+21-29
Original file line numberDiff line numberDiff line change
@@ -5,33 +5,33 @@
55
from migen.fhdl.module import Module
66

77
class M1CRG(Module):
8-
def __init__(self, infreq, outfreq1x):
9-
self.clk50_pad = Signal()
10-
self.trigger_reset = Signal()
11-
12-
self.eth_rx_clk_pad = Signal()
13-
self.eth_tx_clk_pad = Signal()
14-
8+
def __init__(self, pads, outfreq1x):
159
self.clock_domains.cd_sys = ClockDomain()
1610
self.clock_domains.cd_sys2x_270 = ClockDomain()
1711
self.clock_domains.cd_sys4x_wr = ClockDomain()
1812
self.clock_domains.cd_sys4x_rd = ClockDomain()
1913
self.clock_domains.cd_eth_rx = ClockDomain()
2014
self.clock_domains.cd_eth_tx = ClockDomain()
2115
self.clock_domains.cd_vga = ClockDomain()
16+
17+
self.clk4x_wr_strb = Signal()
18+
self.clk4x_rd_strb = Signal()
19+
20+
###
2221

22+
infreq = 50*1000000
2323
ratio = Fraction(outfreq1x)/Fraction(infreq)
2424
in_period = float(Fraction(1000000000)/Fraction(infreq))
2525

26-
inst_items = [
26+
self.specials += Instance("m1crg",
2727
Instance.Parameter("in_period", in_period),
2828
Instance.Parameter("f_mult", ratio.numerator),
2929
Instance.Parameter("f_div", ratio.denominator),
30-
Instance.Input("clk50_pad", self.clk50_pad),
31-
Instance.Input("trigger_reset", self.trigger_reset),
30+
Instance.Input("clk50_pad", pads.clk50),
31+
Instance.Input("trigger_reset", pads.trigger_reset),
3232

33-
Instance.Input("eth_rx_clk_pad", self.eth_rx_clk_pad),
34-
Instance.Input("eth_tx_clk_pad", self.eth_tx_clk_pad),
33+
Instance.Input("eth_rx_clk_pad", pads.eth_rx_clk),
34+
Instance.Input("eth_tx_clk_pad", pads.eth_tx_clk),
3535

3636
Instance.Output("sys_clk", self.cd_sys.clk),
3737
Instance.Output("sys_rst", self.cd_sys.rst),
@@ -40,20 +40,12 @@ def __init__(self, infreq, outfreq1x):
4040
Instance.Output("clk4x_rd", self.cd_sys4x_rd.clk),
4141
Instance.Output("eth_rx_clk", self.cd_eth_rx.clk),
4242
Instance.Output("eth_tx_clk", self.cd_eth_tx.clk),
43-
Instance.Output("vga_clk", self.cd_vga.clk)
44-
]
45-
46-
for name in [
47-
"norflash_rst_n",
48-
"clk4x_wr_strb",
49-
"clk4x_rd_strb",
50-
"ddr_clk_pad_p",
51-
"ddr_clk_pad_n",
52-
"eth_phy_clk_pad",
53-
"vga_clk_pad"
54-
]:
55-
s = Signal(name=name)
56-
setattr(self, name, s)
57-
inst_items.append(Instance.Output(name, s))
58-
59-
self.specials += Instance("m1crg", *inst_items)
43+
Instance.Output("vga_clk", self.cd_vga.clk),
44+
45+
Instance.Output("clk4x_wr_strb", self.clk4x_wr_strb),
46+
Instance.Output("clk4x_rd_strb", self.clk4x_rd_strb),
47+
Instance.Output("norflash_rst_n", pads.norflash_rst_n),
48+
Instance.Output("ddr_clk_pad_p", pads.ddr_clk_p),
49+
Instance.Output("ddr_clk_pad_n", pads.ddr_clk_n),
50+
Instance.Output("eth_phy_clk_pad", pads.eth_phy_clk),
51+
Instance.Output("vga_clk_pad", pads.vga_clk))

‎milkymist/minimac3/__init__.py

+10-23
Original file line numberDiff line numberDiff line change
@@ -8,20 +8,7 @@
88
_count_width = 11
99

1010
class MiniMAC(Module, AutoReg):
11-
def __init__(self):
12-
# PHY signals
13-
self.phy_tx_clk = Signal()
14-
self.phy_tx_data = Signal(4)
15-
self.phy_tx_en = Signal()
16-
self.phy_tx_er = Signal()
17-
self.phy_rx_clk = Signal()
18-
self.phy_rx_data = Signal(4)
19-
self.phy_dv = Signal()
20-
self.phy_rx_er = Signal()
21-
self.phy_col = Signal()
22-
self.phy_crs = Signal()
23-
self.phy_rst_n = Signal()
24-
11+
def __init__(self, pads):
2512
# CPU interface
2613
self._phy_reset = RegisterField(reset=1)
2714
self._rx_count_0 = RegisterField(_count_width, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
@@ -48,7 +35,7 @@ def __init__(self):
4835
rx_pending_0_r = Signal()
4936
rx_pending_1_r = Signal()
5037
self.comb += [
51-
self.phy_rst_n.eq(~self._phy_reset.field.r),
38+
pads.rst_n.eq(~self._phy_reset.field.r),
5239

5340
rx_ready_0.eq(init | (rx_pending_0_r & ~rx_pending_0)),
5441
rx_ready_1.eq(init | (rx_pending_1_r & ~rx_pending_1)),
@@ -85,12 +72,12 @@ def __init__(self):
8572
Instance.Output("wb_ack_o", self.membus.ack),
8673

8774
Instance.Input("phy_tx_clk", ClockSignal("eth_tx")),
88-
Instance.Output("phy_tx_data", self.phy_tx_data),
89-
Instance.Output("phy_tx_en", self.phy_tx_en),
90-
Instance.Output("phy_tx_er", self.phy_tx_er),
75+
Instance.Output("phy_tx_data", pads.tx_data),
76+
Instance.Output("phy_tx_en", pads.tx_en),
77+
Instance.Output("phy_tx_er", pads.tx_er),
9178
Instance.Input("phy_rx_clk", ClockSignal("eth_rx")),
92-
Instance.Input("phy_rx_data", self.phy_rx_data),
93-
Instance.Input("phy_dv", self.phy_dv),
94-
Instance.Input("phy_rx_er", self.phy_rx_er),
95-
Instance.Input("phy_col", self.phy_col),
96-
Instance.Input("phy_crs", self.phy_crs))
79+
Instance.Input("phy_rx_data", pads.rx_data),
80+
Instance.Input("phy_dv", pads.dv),
81+
Instance.Input("phy_rx_er", pads.rx_er),
82+
Instance.Input("phy_col", pads.col),
83+
Instance.Input("phy_crs", pads.crs))

‎milkymist/norflash/__init__.py

+9-13
Original file line numberDiff line numberDiff line change
@@ -4,25 +4,21 @@
44
from migen.genlib.misc import timeline
55

66
class NorFlash(Module):
7-
def __init__(self, adr_width, rd_timing):
7+
def __init__(self, pads, rd_timing):
88
self.bus = wishbone.Interface()
9-
self.adr = Signal(adr_width-1)
10-
self.d = Signal(16)
11-
self.oe_n = Signal()
12-
self.we_n = Signal()
13-
self.ce_n = Signal()
149

1510
###
16-
17-
self.comb += [self.oe_n.eq(0), self.we_n.eq(1),
18-
self.ce_n.eq(0)]
11+
12+
adr_width = len(pads.adr) + 1
13+
self.comb += [pads.oe_n.eq(0), pads.we_n.eq(1),
14+
pads.ce_n.eq(0)]
1915
self.sync += timeline(self.bus.cyc & self.bus.stb, [
20-
(0, [self.adr.eq(Cat(0, self.bus.adr[:adr_width-2]))]),
16+
(0, [pads.adr.eq(Cat(0, self.bus.adr[:adr_width-2]))]),
2117
(rd_timing, [
22-
self.bus.dat_r[16:].eq(self.d),
23-
self.adr.eq(Cat(1, self.bus.adr[:adr_width-2]))]),
18+
self.bus.dat_r[16:].eq(pads.d),
19+
pads.adr.eq(Cat(1, self.bus.adr[:adr_width-2]))]),
2420
(2*rd_timing, [
25-
self.bus.dat_r[:16].eq(self.d),
21+
self.bus.dat_r[:16].eq(pads.d),
2622
self.bus.ack.eq(1)]),
2723
(2*rd_timing + 1, [
2824
self.bus.ack.eq(0)])

‎milkymist/s6ddrphy/__init__.py

+26-27
Original file line numberDiff line numberDiff line change
@@ -4,40 +4,39 @@
44
from migen.bus import dfi
55

66
class S6DDRPHY(Module):
7-
def __init__(self, a, ba, d):
7+
def __init__(self, pads):
8+
self.dfi = dfi.Interface(len(pads.a), len(pads.ba), 2*len(pads.dq), 2)
9+
self.clk4x_wr_strb = Signal()
10+
self.clk4x_rd_strb = Signal()
11+
12+
###
13+
814
inst_items = [
9-
Instance.Parameter("NUM_AD", a),
10-
Instance.Parameter("NUM_BA", ba),
11-
Instance.Parameter("NUM_D", d),
15+
Instance.Parameter("NUM_AD", len(pads.a)),
16+
Instance.Parameter("NUM_BA", len(pads.ba)),
17+
Instance.Parameter("NUM_D", 2*len(pads.dq)),
18+
1219
Instance.Input("sys_clk", ClockSignal()),
1320
Instance.Input("clk2x_270", ClockSignal("sys2x_270")),
1421
Instance.Input("clk4x_wr", ClockSignal("sys4x_wr")),
15-
Instance.Input("clk4x_rd", ClockSignal("sys4x_rd"))
22+
Instance.Input("clk4x_rd", ClockSignal("sys4x_rd")),
23+
24+
Instance.Input("clk4x_wr_strb", self.clk4x_wr_strb),
25+
Instance.Input("clk4x_rd_strb", self.clk4x_rd_strb),
26+
27+
Instance.Output("sd_a", pads.a),
28+
Instance.Output("sd_ba", pads.ba),
29+
Instance.Output("sd_cs_n", pads.cs_n),
30+
Instance.Output("sd_cke", pads.cke),
31+
Instance.Output("sd_ras_n", pads.ras_n),
32+
Instance.Output("sd_cas_n", pads.cas_n),
33+
Instance.Output("sd_we_n", pads.we_n),
34+
Instance.InOut("sd_dq", pads.dq),
35+
Instance.Output("sd_dm", pads.dm),
36+
Instance.InOut("sd_dqs", pads.dqs)
1637
]
17-
for name, width, cl in [
18-
("clk4x_wr_strb", 1, Instance.Input),
19-
("clk4x_rd_strb", 1, Instance.Input),
20-
21-
("sd_a", a, Instance.Output),
22-
("sd_ba", ba, Instance.Output),
23-
("sd_cs_n", 1, Instance.Output),
24-
("sd_cke", 1, Instance.Output),
25-
("sd_ras_n", 1, Instance.Output),
26-
("sd_cas_n", 1, Instance.Output),
27-
("sd_we_n", 1, Instance.Output),
28-
("sd_dq", d//2, Instance.InOut),
29-
("sd_dm", d//16, Instance.Output),
30-
("sd_dqs", d//16, Instance.InOut)
31-
32-
]:
33-
s = Signal(width, name=name)
34-
setattr(self, name, s)
35-
inst_items.append(cl(name, s))
36-
37-
self.dfi = dfi.Interface(a, ba, d, 2)
3838
inst_items += [Instance.Input(name, signal)
3939
for name, signal in self.dfi.get_standard_names(True, False)]
4040
inst_items += [Instance.Output(name, signal)
4141
for name, signal in self.dfi.get_standard_names(False, True)]
42-
4342
self.specials += Instance("s6ddrphy", *inst_items)

‎milkymist/uart/__init__.py

+8-9
Original file line numberDiff line numberDiff line change
@@ -5,20 +5,19 @@
55
from migen.bank.eventmanager import *
66

77
class UART(Module, AutoReg):
8-
def __init__(self, clk_freq, baud=115200):
8+
def __init__(self, pads, clk_freq, baud=115200):
99
self._rxtx = RegisterRaw(8)
1010
self._divisor = RegisterField(16, reset=int(clk_freq/baud/16))
1111

1212
self.submodules.ev = EventManager()
1313
self.ev.tx = EventSourceLevel()
1414
self.ev.rx = EventSourcePulse()
1515
self.ev.finalize()
16-
17-
self.tx = Signal(reset=1)
18-
self.rx = Signal()
1916

2017
###
2118

19+
pads.tx.reset = 1
20+
2221
enable16 = Signal()
2322
enable16_counter = Signal(16)
2423
self.comb += enable16.eq(enable16_counter == 0)
@@ -39,18 +38,18 @@ def __init__(self, clk_freq, baud=115200):
3938
tx_bitcount.eq(0),
4039
tx_count16.eq(1),
4140
tx_busy.eq(1),
42-
self.tx.eq(0)
41+
pads.tx.eq(0)
4342
).Elif(enable16 & tx_busy,
4443
tx_count16.eq(tx_count16 + 1),
4544
If(tx_count16 == 0,
4645
tx_bitcount.eq(tx_bitcount + 1),
4746
If(tx_bitcount == 8,
48-
self.tx.eq(1)
47+
pads.tx.eq(1)
4948
).Elif(tx_bitcount == 9,
50-
self.tx.eq(1),
49+
pads.tx.eq(1),
5150
tx_busy.eq(0)
5251
).Else(
53-
self.tx.eq(tx_reg[0]),
52+
pads.tx.eq(tx_reg[0]),
5453
tx_reg.eq(Cat(tx_reg[1:], 0))
5554
)
5655
)
@@ -59,7 +58,7 @@ def __init__(self, clk_freq, baud=115200):
5958

6059
# RX
6160
rx = Signal()
62-
self.specials += MultiReg(self.rx, rx, "sys")
61+
self.specials += MultiReg(pads.rx, rx)
6362
rx_r = Signal()
6463
rx_reg = Signal(8)
6564
rx_bitcount = Signal(4)

‎top.py

+25-12
Original file line numberDiff line numberDiff line change
@@ -11,8 +11,9 @@
1111
identifier, timer, minimac3, framebuffer, asmiprobe, dvisampler
1212
from cif import get_macros
1313

14-
MHz = 1000000
15-
clk_freq = (83 + Fraction(1, 3))*MHz
14+
version = get_macros("common/version.h")["VERSION"][1:-1]
15+
16+
clk_freq = (83 + Fraction(1, 3))*1000000
1617
sram_size = 4096 # in bytes
1718
l2_size = 8192 # in bytes
1819

@@ -47,7 +48,19 @@ def ns(t, margin=True):
4748
write_time=16
4849
)
4950

50-
version = get_macros("common/version.h")["VERSION"][1:-1]
51+
class M1ClockPads:
52+
def __init__(self, platform):
53+
self.clk50 = platform.request("clk50")
54+
self.trigger_reset = platform.request("user_btn", 1)
55+
self.norflash_rst_n = platform.request("norflash_rst_n")
56+
self.vga_clk = platform.request("vga_clock")
57+
ddram_clock = platform.request("ddram_clock")
58+
self.ddr_clk_p = ddram_clock.p
59+
self.ddr_clk_n = ddram_clock.n
60+
eth_clocks = platform.request("eth_clocks")
61+
self.eth_phy_clk = eth_clocks.phy
62+
self.eth_rx_clk = eth_clocks.rx
63+
self.eth_tx_clk = eth_clocks.tx
5164

5265
class SoC(Module):
5366
csr_base = 0xe0000000
@@ -71,7 +84,7 @@ class SoC(Module):
7184
"minimac": 2,
7285
}
7386

74-
def __init__(self):
87+
def __init__(self, platform):
7588
#
7689
# ASMI
7790
#
@@ -83,7 +96,7 @@ def __init__(self):
8396
#
8497
# DFI
8598
#
86-
self.submodules.ddrphy = s6ddrphy.S6DDRPHY(sdram_geom.mux_a, sdram_geom.bank_a, sdram_phy.dfi_d)
99+
self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"))
87100
self.submodules.dfii = dfii.DFIInjector(sdram_geom.mux_a, sdram_geom.bank_a, sdram_phy.dfi_d,
88101
sdram_phy.nphases)
89102
self.submodules.dficon0 = dfi.Interconnect(self.dfii.master, self.ddrphy.dfi)
@@ -93,9 +106,9 @@ def __init__(self):
93106
# WISHBONE
94107
#
95108
self.submodules.cpu = lm32.LM32()
96-
self.submodules.norflash = norflash.NorFlash(25, 12)
109+
self.submodules.norflash = norflash.NorFlash(platform.request("norflash"), 12)
97110
self.submodules.sram = wishbone.SRAM(sram_size)
98-
self.submodules.minimac = minimac3.MiniMAC()
111+
self.submodules.minimac = minimac3.MiniMAC(platform.request("eth"))
99112
self.submodules.wishbone2asmi = wishbone2asmi.WB2ASMI(l2_size//4, asmiport_wb)
100113
self.submodules.wishbone2csr = wishbone2csr.WB2CSR()
101114

@@ -121,13 +134,13 @@ def __init__(self):
121134
#
122135
# CSR
123136
#
124-
self.submodules.uart = uart.UART(clk_freq, baud=115200)
137+
self.submodules.uart = uart.UART(platform.request("serial"), clk_freq, baud=115200)
125138
self.submodules.identifier = identifier.Identifier(0x4D31, version, int(clk_freq))
126139
self.submodules.timer0 = timer.Timer()
127-
self.submodules.fb = framebuffer.Framebuffer(asmiport_fb)
140+
self.submodules.fb = framebuffer.Framebuffer(platform.request("vga"), asmiport_fb)
128141
self.submodules.asmiprobe = asmiprobe.ASMIprobe(self.asmicon.hub)
129-
self.submodules.dvisampler0 = dvisampler.DVISampler("02")
130-
self.submodules.dvisampler1 = dvisampler.DVISampler("02")
142+
self.submodules.dvisampler0 = dvisampler.DVISampler(platform.request("dvi_in", 0))
143+
self.submodules.dvisampler1 = dvisampler.DVISampler(platform.request("dvi_in", 1))
131144

132145
self.submodules.csrbankarray = csrgen.BankArray(self,
133146
lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override])
@@ -142,7 +155,7 @@ def __init__(self):
142155
#
143156
# Clocking
144157
#
145-
self.submodules.crg = m1crg.M1CRG(50*MHz, clk_freq)
158+
self.submodules.crg = m1crg.M1CRG(M1ClockPads(platform), clk_freq)
146159
self.comb += [
147160
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
148161
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb)

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