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base repository: m-labs/misoc
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head repository: m-labs/misoc
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compare: 784e96bb8764
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  • 2 commits
  • 1 file changed
  • 1 contributor

Commits on May 5, 2013

  1. build.py: support single DVI sampler

    Sebastien Bourdeauducq committed May 5, 2013
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    11cbdf0 View commit details
  2. build.py: LOC clock generator components to limit breakage of the ISE…

    … shitware
    Sebastien Bourdeauducq committed May 5, 2013
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    784e96b View commit details
Showing with 3 additions and 0 deletions.
  1. +3 −0 build.py
3 changes: 3 additions & 0 deletions build.py
Original file line number Diff line number Diff line change
@@ -18,6 +18,8 @@ def main():
""", clk50=platform.lookup_request("clk50"))

platform.add_platform_command("""
INST "m1crg/pll" LOC="PLL_ADV_X0Y1";
INST "m1crg/vga_clock_gen" LOC="DCM_X0Y6";
INST "m1crg/wr_bufpll" LOC = "BUFPLL_X0Y2";
INST "m1crg/rd_bufpll" LOC = "BUFPLL_X0Y3";
@@ -50,6 +52,7 @@ def main():
NET "{dviclk0}" CLOCK_DEDICATED_ROUTE = FALSE;
TIMESPEC "TSdviclk0" = PERIOD "GRPdviclk0" 26.7 ns HIGH 50%;
""", dviclk0=platform.lookup_request("dvi_in", 0).clk)
if hasattr(soc, "dvisampler1"):
platform.add_platform_command("""
NET "{dviclk1}" TNM_NET = "GRPdviclk1";
NET "{dviclk1}" CLOCK_DEDICATED_ROUTE = FALSE;