Skip to content

Commit 582617f

Browse files
fallenfallen
committedSep 21, 2012
Remove all uses of TLBCTRL CSR register, use PSW instead from now on
1 parent c4b1a04 commit 582617f

File tree

4 files changed

+43
-50
lines changed

4 files changed

+43
-50
lines changed
 

‎software/bios/main.c

+4-3
Original file line numberDiff line numberDiff line change
@@ -46,7 +46,7 @@
4646
enum {
4747
CSR_IE = 1, CSR_IM, CSR_IP, CSR_ICC, CSR_DCC, CSR_CC, CSR_CFG, CSR_EBA,
4848
CSR_DC, CSR_DEBA, CSR_JTX, CSR_JRX, CSR_BP0, CSR_BP1, CSR_BP2, CSR_BP3,
49-
CSR_WP0, CSR_WP1, CSR_WP2, CSR_WP3, CSR_TLBCTRL, CSR_TLBVADDR, CSR_TLBPADDR
49+
CSR_WP0, CSR_WP1, CSR_WP2, CSR_WP3, CSR_PSW, CSR_TLBVADDR, CSR_TLBPADDR
5050
};
5151

5252
/* General address space functions */
@@ -233,7 +233,7 @@ static int parse_csr(const char *csr)
233233
if(!strcmp(csr, "wp1")) return CSR_WP1;
234234
if(!strcmp(csr, "wp2")) return CSR_WP2;
235235
if(!strcmp(csr, "wp3")) return CSR_WP3;
236-
if(!strcmp(csr, "tlbctrl")) return CSR_TLBCTRL;
236+
if(!strcmp(csr, "psw")) return CSR_PSW;
237237
if(!strcmp(csr, "tlbvaddr")) return CSR_TLBVADDR;
238238
if(!strcmp(csr, "tlbpaddr")) return CSR_TLBPADDR;
239239

@@ -266,6 +266,7 @@ static void rcsr(char *csr)
266266
case CSR_DEBA: asm volatile ("rcsr %0,deba":"=r"(value)); break;
267267
case CSR_JTX: asm volatile ("rcsr %0,jtx":"=r"(value)); break;
268268
case CSR_JRX: asm volatile ("rcsr %0,jrx":"=r"(value)); break;
269+
case CSR_PSW: asm volatile ("rcsr %0,psw":"=r"(value)); break;
269270
default: printf("csr write only\n"); return;
270271
}
271272

@@ -312,7 +313,7 @@ static void wcsr(char *csr, char *value)
312313
case CSR_WP1: asm volatile ("wcsr wp1,%0"::"r"(value2)); break;
313314
case CSR_WP2: asm volatile ("wcsr wp2,%0"::"r"(value2)); break;
314315
case CSR_WP3: asm volatile ("wcsr wp3,%0"::"r"(value2)); break;
315-
case CSR_TLBCTRL: asm volatile ("wcsr tlbctrl,%0"::"r"(value2)); break;
316+
case CSR_PSW: asm volatile ("wcsr psw,%0"::"r"(value2)); break;
316317
case CSR_TLBVADDR: asm volatile ("wcsr tlbvaddr,%0"::"r"(value2)); break;
317318
case CSR_TLBPADDR: asm volatile ("wcsr tlbpaddr,%0"::"r"(value2)); break;
318319
default: printf("csr read only\n"); return;

‎software/bios/mmu_test_gen.c

+3-3
Original file line numberDiff line numberDiff line change
@@ -8,9 +8,9 @@ static inline void generate_test(int i, int j) {
88
int k;
99

1010
puts("asm volatile(");
11-
puts("\t\"xor r11, r11, r11\\n\\t\"");
12-
puts("\t\"ori r11, r11, 0x11\\n\\t\"");
13-
puts("\t\"wcsr tlbctrl, r11\\n\\t\"");
11+
puts("\t\"rcsr r11, PSW\\n\\t\"");
12+
puts("\t\"ori r11, r11, 64\\n\\t\"");
13+
puts("\t\"wcsr PSW, r11\\n\\t\"");
1414
puts("\t\"xor r0, r0, r0\\n\\t\"");
1515
puts("\t\"xor r0, r0, r0\\n\\t\"");
1616
puts("\t\"xor r0, r0, r0\\n\\t\"");

‎software/include/hal/mmu.h

+12-17
Original file line numberDiff line numberDiff line change
@@ -46,44 +46,39 @@ struct mmu_mapping {
4646
};
4747

4848
#define enable_dtlb() do { \
49-
asm volatile ("xor r11, r11, r11\n\t" \
50-
"ori r11, r11, 0x11\n\t" \
51-
"wcsr tlbctrl, r11\n\t" \
52-
"xor r0, r0, r0":::"r11"); \
49+
asm volatile ("rcsr r11, PSW\n\t" \
50+
"ori r11, r11, 64\n\t" \
51+
"wcsr PSW, r11\n\t" \
52+
"xor r0, r0, r0" ::: "r11"); \
5353
} while(0);
5454

5555
#define disable_dtlb() do { \
56-
asm volatile ("xor r11, r11, r11\n\t" \
57-
"ori r11, r11, 0x9\n\t" \
58-
"wcsr tlbctrl, r11\n\t" \
56+
asm volatile ("rcsr r11, PSW\n\t" \
57+
"mvi r10, ~(64)\n\t" \
58+
"and r11, r11, r10\n\t" \
59+
"wcsr PSW, r11\n\t" \
5960
"xor r0, r0, r0\n\t" \
6061
"xor r0, r0, r0\n\t" \
61-
"xor r0, r0, r0":::"r11"); \
62+
"xor r0, r0, r0" ::: "r11", "r10"); \
6263
} while(0);
6364

6465
#define enable_itlb() do { \
65-
asm volatile ("xor r11, r11, r11\n\t" \
66-
"ori r11, r11, 0x10\n\t" \
67-
"wcsr tlbctrl, r11\n\t" \
66+
asm volatile ("rcsr r11, PSW\n\t" \
67+
"ori r11, r11, 0x8\n\t" \
68+
"wcsr PSW, r11\n\t" \
6869
"xor r0, r0, r0\n\t" \
6970
"xor r0, r0, r0\n\t" \
7071
"xor r0, r0, r0\n\t" \
7172
"xor r0, r0, r0\n\t":::"r11"); \
7273
} while(0);
7374

74-
#define LM32_CSR_PSW_ITLBE "(0x8)"
75-
7675
#define disable_itlb() do { \
7776
asm volatile ("rcsr r11, PSW\n\t" \
7877
"mvi r10, ~(0x8)\n\t" \
7978
"and r11, r11, r10\n\t" \
8079
"wcsr PSW, r11\n\t" ::: "r10", "r11"); \
8180
} while (0);
8281

83-
// FIXME : We MUST replace the following macro with a function which
84-
// enables ITLB using two different methods depending on whether
85-
// branch will be predicted as taken or non-taken
86-
8782
#define call_function_with_itlb_enabled(function) do { \
8883
asm volatile ("rcsr r11, PSW\n\t" \
8984
"ori r11, r11, 0x8\n\t" \

‎software/libhal/mmu.c

+24-27
Original file line numberDiff line numberDiff line change
@@ -36,11 +36,10 @@ inline void mmu_dtlb_map(unsigned int vpfn, unsigned int pfn)
3636

3737
asm volatile ("ori %0, %0, 1\n\t"
3838
"wcsr tlbpaddr, %0" :: "r"(pfn) : );
39-
39+
/*
4040
asm volatile ("xor r11, r11, r11\n\t"
4141
"ori r11, r11, 0x5\n\t"
42-
"wcsr tlbctrl, r11" ::: "r11");
43-
42+
"wcsr tlbctrl, r11" ::: "r11"); */
4443
}
4544

4645
inline void mmu_itlb_map(unsigned int vpfn, unsigned int pfn)
@@ -50,42 +49,34 @@ inline void mmu_itlb_map(unsigned int vpfn, unsigned int pfn)
5049

5150
asm volatile ("wcsr tlbpaddr, %0" :: "r"(get_pfn(pfn)) : );
5251

53-
asm volatile ("xor r11, r11, r11\n\t"
52+
/* asm volatile ("xor r11, r11, r11\n\t"
5453
"ori r11, r11, 0x4\n\t"
55-
"wcsr tlbctrl, r11" ::: "r11");
54+
"wcsr tlbctrl, r11" ::: "r11"); */
5655
}
5756

5857
inline void mmu_dtlb_invalidate_line(unsigned int vaddr)
5958
{
60-
asm volatile ("ori %0, %0, 1\n\t"
59+
asm volatile ("ori %0, %0, 0x21\n\t"
6160
"wcsr tlbvaddr, %0" :: "r"(vaddr) : );
62-
63-
asm volatile ("xor r11, r11, r11\n\t"
64-
"ori r11, r11, 0x21\n\t"
65-
"wcsr tlbctrl, r11" ::: "r11");
6661
}
6762

6863
inline void mmu_itlb_invalidate_line(unsigned int vaddr)
6964
{
70-
asm volatile ("ori %0, %0, 0\n\t"
65+
asm volatile ("ori %0, %0, 0x20\n\t"
7166
"wcsr tlbvaddr, %0" :: "r"(vaddr) : );
72-
73-
asm volatile ("xor r11, r11, r11\n\t"
74-
"ori r11, r11, 0x20\n\t"
75-
"wcsr tlbctrl, r11" ::: "r11");
7667
}
7768

7869
inline void mmu_dtlb_invalidate(void)
7970
{
8071
register unsigned int cmd = DTLB_CTRL_FLUSH_CMD;
81-
asm volatile("wcsr tlbctrl, %0" :: "r"(cmd) : );
72+
// asm volatile("wcsr tlbctrl, %0" :: "r"(cmd) : );
8273

8374
}
8475

8576
inline void mmu_itlb_invalidate(void)
8677
{
8778
register unsigned int cmd = ITLB_CTRL_FLUSH_CMD;
88-
asm volatile("wcsr tlbctrl, %0" :: "r"(cmd) : );
79+
// asm volatile("wcsr tlbctrl, %0" :: "r"(cmd) : );
8980

9081
}
9182

@@ -103,11 +94,17 @@ unsigned int read_word_with_mmu_enabled(unsigned int vaddr)
10394
cmd1 = DTLB_CTRL_ENABLE_CMD;
10495
cmd2 = DTLB_CTRL_DISABLE_CMD;
10596

106-
asm volatile("wcsr tlbctrl, %2\n\t" // Activates the MMU
97+
asm volatile("rcsr r11, PSW\n\t"
98+
"ori r11, r11, 64\n\t"
99+
"wcsr PSW, r11\n\t" // Activates the MMU
100+
//"wcsr tlbctrl, %2\n\t" // Activates the MMU
107101
"xor r0, r0, r0\n\t"
108102
"lw %0, (%1+0)\n\t" // Reads from virtual address "addr"
109-
"wcsr tlbctrl, %3\n\t" // Disactivates the MMU
110-
"xor r0, r0, r0\n\t" : "=&r"(data) : "r"(vaddr), "r"(cmd1), "r"(cmd2) :
103+
"mvi r10, ~(64)\n\t"
104+
"and r11, r11, r10\n\t"
105+
"wcsr PSW, r11\n\t" // Disactivates the MMU
106+
//"wcsr tlbctrl, %3\n\t" // Disactivates the MMU
107+
"xor r0, r0, r0\n\t" : "=&r"(data) : "r"(vaddr)/*, "r"(cmd1), "r"(cmd2)*/ : "r11", "r10"
111108
);
112109

113110
return data;
@@ -116,15 +113,15 @@ unsigned int read_word_with_mmu_enabled(unsigned int vaddr)
116113
unsigned int write_word_with_mmu_enabled(register unsigned int vaddr, register unsigned int data)
117114
{
118115
asm volatile(
119-
"xor r11, r11, r11\n\t"
120-
"ori r11, r11, 0x11\n\t"
121-
"wcsr tlbctrl, r11\n\t" // Activates the MMU
116+
"rcsr r11, PSW\n\t"
117+
"ori r11, r11, 64\n\t"
118+
"wcsr PSW, r11\n\t" // Activates the MMU
122119
"xor r0, r0, r0\n\t"
123120
"sw (%0 + 0), %1\n\t" // Reads from virtual address "addr"
124-
"xor r11, r11, r11\n\t"
125-
"ori r11, r11, 0x9\n\t"
126-
"wcsr tlbctrl, r11\n\t" // Disactivates the MMU
127-
"xor r0, r0, r0\n\t" :: "r"(vaddr), "r"(data) : "r11"
121+
"mvi r10, ~(64)\n\t"
122+
"and r11, r11, r10\n\t"
123+
"wcsr PSW, r11\n\t" // Disactivates the MMU
124+
"xor r0, r0, r0\n\t" :: "r"(vaddr), "r"(data) : "r11", "r10"
128125
);
129126
}
130127
/*

0 commit comments

Comments
 (0)
Please sign in to comment.