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author
Sebastien Bourdeauducq
committedMar 10, 2013
Use new module, autoreg and eventmanager Migen APIs
·
0.120.1
1 parent 2059592 commit a9b7235

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21 files changed

+421
-568
lines changed

21 files changed

+421
-568
lines changed
 

‎common/csrbase.h

+7-7
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,12 @@
11
#ifndef __CSRBASE_H
22
#define __CSRBASE_H
33

4-
#define UART_BASE 0xe0000000
5-
#define DFII_BASE 0xe0000800
6-
#define ID_BASE 0xe0001000
7-
#define TIMER0_BASE 0xe0001800
8-
#define MINIMAC_BASE 0xe0002000
9-
#define FB_BASE 0xe0002800
10-
#define ASMIPROBE_BASE 0xe0003000
4+
#define UART_BASE 0xe0000000
5+
#define DFII_BASE 0xe0000800
6+
#define IDENTIFIER_BASE 0xe0001000
7+
#define TIMER0_BASE 0xe0001800
8+
#define MINIMAC_BASE 0xe0002000
9+
#define FB_BASE 0xe0002800
10+
#define ASMIPROBE_BASE 0xe0003000
1111

1212
#endif /* __CSRBASE_H */

‎milkymist/asmicon/__init__.py

+7-19
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
11
from migen.fhdl.structure import *
2+
from migen.fhdl.module import Module
23
from migen.bus import dfi, asmibus
34

45
from milkymist.asmicon.refresher import *
@@ -34,13 +35,12 @@ def __init__(self, tRP, tRCD, tWR, tREFI, tRFC, CL, rd_delay, read_time, write_t
3435
self.write_time = write_time
3536
self.slot_time = slot_time
3637

37-
class ASMIcon:
38+
class ASMIcon(Module):
3839
def __init__(self, phy_settings, geom_settings, timing_settings, full_selector=False):
3940
self.phy_settings = phy_settings
4041
self.geom_settings = geom_settings
4142
self.timing_settings = timing_settings
4243
self.full_selector = full_selector
43-
self.finalized = False
4444

4545
self.dfi = dfi.Interface(self.geom_settings.mux_a,
4646
self.geom_settings.bank_a,
@@ -50,26 +50,14 @@ def __init__(self, phy_settings, geom_settings, timing_settings, full_selector=F
5050
self.address_align = log2_int(burst_length)
5151
aw = self.geom_settings.bank_a + self.geom_settings.row_a + self.geom_settings.col_a - self.address_align
5252
dw = self.phy_settings.dfi_d*self.phy_settings.nphases
53-
self.hub = asmibus.Hub(aw, dw, self.timing_settings.slot_time)
53+
self.submodules.hub = asmibus.Hub(aw, dw, self.timing_settings.slot_time)
5454

55-
def finalize(self):
56-
if self.finalized:
57-
raise FinalizeError
58-
self.finalized = True
59-
self.hub.finalize()
55+
def do_finalize(self):
6056
slots = self.hub.get_slots()
61-
self.refresher = Refresher(self.geom_settings.mux_a, self.geom_settings.bank_a,
57+
self.submodules.refresher = Refresher(self.geom_settings.mux_a, self.geom_settings.bank_a,
6258
self.timing_settings.tRP, self.timing_settings.tREFI, self.timing_settings.tRFC)
63-
self.bank_machines = [BankMachine(self.geom_settings, self.timing_settings, self.address_align, i, slots, self.full_selector)
59+
self.submodules.bank_machines = [BankMachine(self.geom_settings, self.timing_settings, self.address_align, i, slots, self.full_selector)
6460
for i in range(2**self.geom_settings.bank_a)]
65-
self.multiplexer = Multiplexer(self.phy_settings, self.geom_settings, self.timing_settings,
61+
self.submodules.multiplexer = Multiplexer(self.phy_settings, self.geom_settings, self.timing_settings,
6662
self.bank_machines, self.refresher,
6763
self.dfi, self.hub)
68-
69-
def get_fragment(self):
70-
if not self.finalized:
71-
raise FinalizeError
72-
return self.hub.get_fragment() + \
73-
self.refresher.get_fragment() + \
74-
sum([bm.get_fragment() for bm in self.bank_machines], Fragment()) + \
75-
self.multiplexer.get_fragment()

‎milkymist/asmicon/bankmachine.py

+75-110
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
11
from migen.fhdl.structure import *
2+
from migen.fhdl.module import Module
23
from migen.bus.asmibus import *
34
from migen.genlib.roundrobin import *
45
from migen.genlib.fsm import FSM
@@ -33,97 +34,81 @@ def col(self, address):
3334
else:
3435
return Cat(Replicate(0, self.address_align), address[:self._b1])
3536

36-
class _Selector:
37+
class _Selector(Module):
3738
def __init__(self, slicer, bankn, slots):
38-
self.slicer = slicer
39-
self.bankn = bankn
40-
self.slots = slots
41-
42-
self.nslots = len(self.slots)
39+
nslots = len(slots)
4340
self.stb = Signal()
4441
self.ack = Signal()
45-
self.tag = Signal(max=self.nslots)
46-
self.adr = Signal(self.slots[0].adr.nbits)
42+
self.tag = Signal(max=nslots)
43+
self.adr = Signal(slots[0].adr.nbits)
4744
self.we = Signal()
4845

4946
# derived classes should drive rr.request
50-
self.rr = RoundRobin(self.nslots, SP_CE)
47+
self.submodules.rr = RoundRobin(nslots, SP_CE)
5148

52-
def get_fragment(self):
53-
comb = []
54-
rr = self.rr
55-
49+
###
50+
5651
# Multiplex
52+
rr = self.rr
5753
state = Signal(2)
58-
comb += [
59-
state.eq(Array(slot.state for slot in self.slots)[rr.grant]),
60-
self.adr.eq(Array(slot.adr for slot in self.slots)[rr.grant]),
61-
self.we.eq(Array(slot.we for slot in self.slots)[rr.grant]),
54+
self.comb += [
55+
state.eq(Array(slot.state for slot in slots)[rr.grant]),
56+
self.adr.eq(Array(slot.adr for slot in slots)[rr.grant]),
57+
self.we.eq(Array(slot.we for slot in slots)[rr.grant]),
6258
self.stb.eq(
63-
(self.slicer.bank(self.adr) == self.bankn) \
59+
(slicer.bank(self.adr) == bankn) \
6460
& (state == SLOT_PENDING)),
6561
rr.ce.eq(self.ack | ~self.stb),
6662
self.tag.eq(rr.grant)
6763
]
68-
comb += [If((rr.grant == i) & self.stb & self.ack, slot.process.eq(1))
69-
for i, slot in enumerate(self.slots)]
70-
71-
return Fragment(comb) + rr.get_fragment()
64+
self.comb += [If((rr.grant == i) & self.stb & self.ack, slot.process.eq(1))
65+
for i, slot in enumerate(slots)]
66+
67+
self.complete_selector(slicer, bankn, slots)
7268

7369
class _SimpleSelector(_Selector):
74-
def get_fragment(self):
75-
comb = []
76-
for i, slot in enumerate(self.slots):
77-
comb.append(self.rr.request[i].eq(
78-
(self.slicer.bank(slot.adr) == self.bankn) & \
79-
(slot.state == SLOT_PENDING)
80-
))
81-
82-
return Fragment(comb) + _Selector.get_fragment(self)
70+
def complete_selector(self, slicer, bankn, slots):
71+
for i, slot in enumerate(slots):
72+
self.comb += self.rr.request[i].eq(
73+
(slicer.bank(slot.adr) == bankn) & \
74+
(slot.state == SLOT_PENDING))
8375

8476
class _FullSelector(_Selector):
85-
def get_fragment(self):
86-
comb = []
87-
sync = []
77+
def complete_selector(self, slicer, bankn, slots):
8878
rr = self.rr
8979

9080
# List outstanding requests for our bank
9181
outstandings = []
92-
for slot in self.slots:
82+
for slot in slots:
9383
outstanding = Signal()
94-
comb.append(outstanding.eq(
95-
(self.slicer.bank(slot.adr) == self.bankn) & \
96-
(slot.state == SLOT_PENDING)
97-
))
84+
self.comb += outstanding.eq(
85+
(slicer.bank(slot.adr) == bankn) & \
86+
(slot.state == SLOT_PENDING))
9887
outstandings.append(outstanding)
9988

10089
# Row tracking
101-
openrow_r = Signal(self.slicer.geom_settings.row_a)
102-
openrow_n = Signal(self.slicer.geom_settings.row_a)
103-
openrow = Signal(self.slicer.geom_settings.row_a)
104-
comb += [
105-
openrow_n.eq(self.slicer.row(self.adr)),
90+
openrow_r = Signal(slicer.geom_settings.row_a)
91+
openrow_n = Signal(slicer.geom_settings.row_a)
92+
openrow = Signal(slicer.geom_settings.row_a)
93+
self.comb += [
94+
openrow_n.eq(slicer.row(self.adr)),
10695
If(self.stb,
10796
openrow.eq(openrow_n)
10897
).Else(
10998
openrow.eq(openrow_r)
11099
)
111100
]
112-
sync += [
113-
If(self.stb & self.ack,
114-
openrow_r.eq(openrow_n)
115-
)
116-
]
101+
self.sync += If(self.stb & self.ack, openrow_r.eq(openrow_n))
117102
hits = []
118-
for slot, os in zip(self.slots, outstandings):
103+
for slot, os in zip(slots, outstandings):
119104
hit = Signal()
120-
comb.append(hit.eq((self.slicer.row(slot.adr) == openrow) & os))
105+
self.comb += hit.eq((slicer.row(slot.adr) == openrow) & os)
121106
hits.append(hit)
122107

123108
# Determine best request
124109
rr = RoundRobin(self.nslots, SP_CE)
125110
has_hit = Signal()
126-
comb.append(has_hit.eq(optree("|", hits)))
111+
self.comb += has_hit.eq(optree("|", hits))
127112

128113
best_hit = [rr.request[i].eq(hit)
129114
for i, hit in enumerate(hits)]
@@ -135,84 +120,72 @@ def get_fragment(self):
135120
*best_fallback
136121
)
137122

138-
if self.slots[0].time:
123+
if slots[0].time:
139124
# Implement anti-starvation timer
140125
matures = []
141-
for slot, os in zip(self.slots, outstandings):
126+
for slot, os in zip(slots, outstandings):
142127
mature = Signal()
143128
comb.append(mature.eq(slot.mature & os))
144129
matures.append(mature)
145130
has_mature = Signal()
146-
comb.append(has_mature.eq(optree("|", matures)))
131+
self.comb += has_mature.eq(optree("|", matures))
147132
best_mature = [rr.request[i].eq(mature)
148133
for i, mature in enumerate(matures)]
149134
select_stmt = If(has_mature, *best_mature).Else(select_stmt)
150-
comb.append(select_stmt)
151-
152-
return Fragment(comb, sync) + _Selector.get_fragment(self)
135+
self.comb += select_stmt
153136

154-
class _Buffer:
137+
class _Buffer(Module):
155138
def __init__(self, source):
156-
self.source = source
157-
158139
self.stb = Signal()
159140
self.ack = Signal()
160-
self.tag = Signal(self.source.tag.bv)
161-
self.adr = Signal(self.source.adr.bv)
141+
self.tag = Signal(source.tag.bv)
142+
self.adr = Signal(source.adr.bv)
162143
self.we = Signal()
163144

164-
def get_fragment(self):
145+
###
146+
165147
en = Signal()
166-
comb = [
148+
self.comb += [
167149
en.eq(self.ack | ~self.stb),
168-
self.source.ack.eq(en)
150+
source.ack.eq(en)
169151
]
170-
sync = [
152+
self.sync += [
171153
If(en,
172-
self.stb.eq(self.source.stb),
173-
self.tag.eq(self.source.tag),
174-
self.adr.eq(self.source.adr),
175-
self.we.eq(self.source.we)
154+
self.stb.eq(source.stb),
155+
self.tag.eq(source.tag),
156+
self.adr.eq(source.adr),
157+
self.we.eq(source.we)
176158
)
177159
]
178-
return Fragment(comb, sync)
179160

180-
class BankMachine:
161+
class BankMachine(Module):
181162
def __init__(self, geom_settings, timing_settings, address_align, bankn, slots, full_selector):
182-
self.geom_settings = geom_settings
183-
self.timing_settings = timing_settings
184-
self.address_align = address_align
185-
self.bankn = bankn
186-
self.slots = slots
187-
self.full_selector = full_selector
188-
189163
self.refresh_req = Signal()
190164
self.refresh_gnt = Signal()
191165
self.cmd = CommandRequestRW(geom_settings.mux_a, geom_settings.bank_a,
192166
bits_for(len(slots)-1))
193167

194-
def get_fragment(self):
195-
comb = []
196-
sync = []
197-
168+
###
169+
198170
# Sub components
199-
slicer = _AddressSlicer(self.geom_settings, self.address_align)
200-
if self.full_selector:
201-
selector = _FullSelector(slicer, self.bankn, self.slots)
202-
buf = _Buffer(selector)
203-
cmdsource = buf
171+
slicer = _AddressSlicer(geom_settings, address_align)
172+
if full_selector:
173+
selector = _FullSelector(slicer, bankn, slots)
174+
self.submodules.buf = _Buffer(selector)
175+
cmdsource = self.buf
204176
else:
205-
selector = _SimpleSelector(slicer, self.bankn, self.slots)
177+
selector = _SimpleSelector(slicer, bankn, slots)
206178
cmdsource = selector
179+
self.submodules += selector
207180

208181
# Row tracking
209182
has_openrow = Signal()
210-
openrow = Signal(self.geom_settings.row_a)
183+
openrow = Signal(geom_settings.row_a)
211184
hit = Signal()
212-
comb.append(hit.eq(openrow == slicer.row(cmdsource.adr)))
185+
self.comb += hit.eq(openrow == slicer.row(cmdsource.adr))
213186
track_open = Signal()
214187
track_close = Signal()
215-
sync += [
188+
self.sync += [
216189
If(track_open,
217190
has_openrow.eq(1),
218191
openrow.eq(slicer.row(cmdsource.adr))
@@ -224,23 +197,23 @@ def get_fragment(self):
224197

225198
# Address generation
226199
s_row_adr = Signal()
227-
comb += [
228-
self.cmd.ba.eq(self.bankn),
200+
self.comb += [
201+
self.cmd.ba.eq(bankn),
229202
If(s_row_adr,
230203
self.cmd.a.eq(slicer.row(cmdsource.adr))
231204
).Else(
232205
self.cmd.a.eq(slicer.col(cmdsource.adr))
233206
)
234207
]
235208

236-
comb.append(self.cmd.tag.eq(cmdsource.tag))
209+
self.comb += self.cmd.tag.eq(cmdsource.tag)
237210

238211
# Respect write-to-precharge specification
239212
precharge_ok = Signal()
240-
t_unsafe_precharge = 2 + self.timing_settings.tWR - 1
213+
t_unsafe_precharge = 2 + timing_settings.tWR - 1
241214
unsafe_precharge_count = Signal(max=t_unsafe_precharge+1)
242-
comb.append(precharge_ok.eq(unsafe_precharge_count == 0))
243-
sync += [
215+
self.comb += precharge_ok.eq(unsafe_precharge_count == 0)
216+
self.sync += [
244217
If(self.cmd.stb & self.cmd.ack & self.cmd.is_write,
245218
unsafe_precharge_count.eq(t_unsafe_precharge)
246219
).Elif(~precharge_ok,
@@ -250,9 +223,10 @@ def get_fragment(self):
250223

251224
# Control and command generation FSM
252225
fsm = FSM("REGULAR", "PRECHARGE", "ACTIVATE", "REFRESH", delayed_enters=[
253-
("TRP", "ACTIVATE", self.timing_settings.tRP-1),
254-
("TRCD", "REGULAR", self.timing_settings.tRCD-1)
226+
("TRP", "ACTIVATE", timing_settings.tRP-1),
227+
("TRCD", "REGULAR", timing_settings.tRCD-1)
255228
])
229+
self.submodules += fsm
256230
fsm.act(fsm.REGULAR,
257231
If(self.refresh_req,
258232
fsm.next_state(fsm.REFRESH)
@@ -298,12 +272,3 @@ def get_fragment(self):
298272
track_close.eq(1),
299273
If(~self.refresh_req, fsm.next_state(fsm.REGULAR))
300274
)
301-
302-
if self.full_selector:
303-
buf_fragment = buf.get_fragment()
304-
else:
305-
buf_fragment = Fragment()
306-
return Fragment(comb, sync) + \
307-
selector.get_fragment() + \
308-
buf_fragment + \
309-
fsm.get_fragment()

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