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Commit 07c3327

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enjoy-digitalsbourdeauducq
enjoy-digital
authored and
sbourdeauducq
committedOct 20, 2014
use new direct access on endpoints
·
0.9.20.1
1 parent ff688fb commit 07c3327

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6 files changed

+23
-23
lines changed

6 files changed

+23
-23
lines changed
 

‎migen/actorlib/crc.py

+5-5
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@ def __init__(self, crc_class, layout):
2929

3030
###
3131

32-
dw = flen(self.sink.payload.d)
32+
dw = flen(self.sink.d)
3333
self.submodules.crc = crc_class(dw)
3434
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
3535

@@ -43,7 +43,7 @@ def __init__(self, crc_class, layout):
4343
)
4444
fsm.act("COPY",
4545
self.crc.ce.eq(self.sink.stb & self.source.ack),
46-
self.crc.d.eq(self.sink.payload.d),
46+
self.crc.d.eq(self.sink.d),
4747
Record.connect(self.sink, self.source),
4848
self.source.eop.eq(0),
4949
If(self.sink.stb & self.sink.eop & self.source.ack,
@@ -55,7 +55,7 @@ def __init__(self, crc_class, layout):
5555
cnt_done = Signal()
5656
fsm.act("INSERT",
5757
self.source.stb.eq(1),
58-
chooser(self.crc.value, cnt, self.source.payload.d, reverse=True),
58+
chooser(self.crc.value, cnt, self.source.d, reverse=True),
5959
If(cnt_done,
6060
self.source.eop.eq(1),
6161
If(self.source.ack, NextState("IDLE"))
@@ -99,7 +99,7 @@ def __init__(self, crc_class, layout):
9999

100100
###
101101

102-
dw = flen(self.sink.payload.d)
102+
dw = flen(self.sink.d)
103103
self.submodules.crc = crc_class(dw)
104104

105105
fsm = FSM(reset_state="IDLE")
@@ -116,7 +116,7 @@ def __init__(self, crc_class, layout):
116116
fsm.act("COPY",
117117
Record.connect(self.sink, self.source),
118118
self.crc.ce.eq(self.sink.stb & (self.sink.ack | self.sink.eop)),
119-
self.crc.d.eq(self.sink.payload.d),
119+
self.crc.d.eq(self.sink.d),
120120
If(self.sink.stb & self.sink.eop,
121121
self.sink.ack.eq(0),
122122
self.source.stb.eq(0),

‎migen/actorlib/dma_lasmi.py

+4-4
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ def __init__(self, lasmim, fifo_depth=None):
2020
self.comb += [
2121
lasmim.we.eq(0),
2222
lasmim.stb.eq(self.address.stb & request_enable),
23-
lasmim.adr.eq(self.address.payload.a),
23+
lasmim.adr.eq(self.address.a),
2424
self.address.ack.eq(lasmim.req_ack & request_enable),
2525
request_issued.eq(lasmim.stb & lasmim.req_ack)
2626
]
@@ -59,7 +59,7 @@ def __init__(self, lasmim, fifo_depth=None):
5959

6060
self.data.stb.eq(fifo.readable),
6161
fifo.re.eq(self.data.ack),
62-
self.data.payload.d.eq(fifo.dout),
62+
self.data.d.eq(fifo.dout),
6363
data_dequeued.eq(self.data.stb & self.data.ack)
6464
]
6565

@@ -80,10 +80,10 @@ def __init__(self, lasmim, fifo_depth=None):
8080
self.comb += [
8181
lasmim.we.eq(1),
8282
lasmim.stb.eq(fifo.writable & self.address_data.stb),
83-
lasmim.adr.eq(self.address_data.payload.a),
83+
lasmim.adr.eq(self.address_data.a),
8484
self.address_data.ack.eq(fifo.writable & lasmim.req_ack),
8585
fifo.we.eq(self.address_data.stb & lasmim.req_ack),
86-
fifo.din.eq(self.address_data.payload.d)
86+
fifo.din.eq(self.address_data.d)
8787
]
8888

8989
data_valid = lasmim.dat_ack

‎migen/actorlib/dma_wishbone.py

+4-4
Original file line numberDiff line numberDiff line change
@@ -21,10 +21,10 @@ def __init__(self):
2121
bus_stb.eq(self.address.stb & (~data_reg_loaded | self.data.ack)),
2222
self.bus.cyc.eq(bus_stb),
2323
self.bus.stb.eq(bus_stb),
24-
self.bus.adr.eq(self.address.payload.a),
24+
self.bus.adr.eq(self.address.a),
2525
self.address.ack.eq(self.bus.ack),
2626
self.data.stb.eq(data_reg_loaded),
27-
self.data.payload.d.eq(data_reg)
27+
self.data.d.eq(data_reg)
2828
]
2929
self.sync += [
3030
If(self.data.ack, data_reg_loaded.eq(0)),
@@ -47,8 +47,8 @@ def __init__(self):
4747
self.bus.we.eq(1),
4848
self.bus.cyc.eq(self.address_data.stb),
4949
self.bus.stb.eq(self.address_data.stb),
50-
self.bus.adr.eq(self.address_data.payload.a),
50+
self.bus.adr.eq(self.address_data.a),
5151
self.bus.sel.eq(0xf),
52-
self.bus.dat_w.eq(self.address_data.payload.d),
52+
self.bus.dat_w.eq(self.address_data.d),
5353
self.address_data.ack.eq(self.bus.ack)
5454
]

‎migen/actorlib/fifo.py

+2-2
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ def __init__(self, fifo_class, layout, depth):
1818
self.fifo.din.eq(self.sink.payload),
1919

2020
self.source.stb.eq(self.fifo.readable),
21-
self.source.payload.eq(self.fifo.dout),
21+
self.source.eq(self.fifo.dout),
2222
self.fifo.re.eq(self.source.ack)
2323
]
2424

@@ -28,4 +28,4 @@ def __init__(self, layout, depth):
2828

2929
class AsyncFIFO(_FIFOActor):
3030
def __init__(self, layout, depth):
31-
_FIFOActor.__init__(self, fifo.AsyncFIFO, layout, depth)
31+
_FIFOActor.__init__(self, fifo.AsyncFIFO, layout, depth)

‎migen/actorlib/misc.py

+4-4
Original file line numberDiff line numberDiff line change
@@ -32,8 +32,8 @@ def __init__(self, nbits, offsetbits=0, step=1):
3232
self.sync += [
3333
If(load,
3434
counter.eq(0),
35-
maximum.eq(self.parameters.payload.maximum),
36-
offset.eq(self.parameters.payload.offset) if offsetbits else None
35+
maximum.eq(self.parameters.maximum),
36+
offset.eq(self.parameters.offset) if offsetbits else None
3737
).Elif(ce,
3838
If(last,
3939
counter.eq(0)
@@ -43,9 +43,9 @@ def __init__(self, nbits, offsetbits=0, step=1):
4343
)
4444
]
4545
if offsetbits:
46-
self.comb += self.source.payload.value.eq(counter + offset)
46+
self.comb += self.source.value.eq(counter + offset)
4747
else:
48-
self.comb += self.source.payload.value.eq(counter)
48+
self.comb += self.source.value.eq(counter)
4949

5050
fsm = FSM()
5151
self.submodules += fsm

‎migen/actorlib/spi.py

+4-4
Original file line numberDiff line numberDiff line change
@@ -128,8 +128,8 @@ def get_csrs(self):
128128

129129
class DMAReadController(_DMAController):
130130
def __init__(self, bus_accessor, *args, **kwargs):
131-
bus_aw = flen(bus_accessor.address.payload.a)
132-
bus_dw = flen(bus_accessor.data.payload.d)
131+
bus_aw = flen(bus_accessor.address.a)
132+
bus_dw = flen(bus_accessor.data.d)
133133
_DMAController.__init__(self, bus_accessor, bus_aw, bus_dw, *args, **kwargs)
134134

135135
g = DataFlowGraph()
@@ -147,8 +147,8 @@ def __init__(self, bus_accessor, *args, **kwargs):
147147

148148
class DMAWriteController(_DMAController):
149149
def __init__(self, bus_accessor, *args, ack_when_inactive=False, **kwargs):
150-
bus_aw = flen(bus_accessor.address_data.payload.a)
151-
bus_dw = flen(bus_accessor.address_data.payload.d)
150+
bus_aw = flen(bus_accessor.address_data.a)
151+
bus_dw = flen(bus_accessor.address_data.d)
152152
_DMAController.__init__(self, bus_accessor, bus_aw, bus_dw, *args, **kwargs)
153153

154154
g = DataFlowGraph()

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