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Commit 411e1af

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author
Sebastien Bourdeauducq
committedDec 16, 2011
Proper reset generation
1 parent 738b45d commit 411e1af

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6 files changed

+103
-11
lines changed

6 files changed

+103
-11
lines changed
 

‎build.py

+1
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@ def add_core_dir(d):
1010
def add_core_files(d, files):
1111
for f in files:
1212
verilog_sources.append(os.path.join("verilog", d, f))
13+
add_core_dir("m1reset")
1314
add_core_files("lm32", ["lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
1415
"lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
1516
"lm32_shifter.v", "lm32_multiplier_spartan6.v", "lm32_mc_arithmetic.v",

‎constraints.py

+6-4
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
def get(ns, norflash0, uart0):
1+
def get(ns, reset0, norflash0, uart0):
22
constraints = []
33
def add(signal, pin, vec=-1, iostandard="LVCMOS33", extra=""):
44
constraints.append((ns.get_name(signal), vec, pin, iostandard, extra))
@@ -8,6 +8,11 @@ def add_vec(signal, pins, iostandard="LVCMOS33", extra=""):
88
add(signal, p, i, iostandard, extra)
99
i += 1
1010

11+
add(reset0.trigger_reset, "AA4")
12+
add(reset0.ac97_rst_n, "D6")
13+
add(reset0.videoin_rst_n, "W17")
14+
add(reset0.flash_rst_n, "P22", extra="SLEW = FAST | DRIVE = 8")
15+
1116
add_vec(norflash0.adr, ["L22", "L20", "K22", "K21", "J19", "H20", "F22",
1217
"F21", "K17", "J17", "E22", "E20", "H18", "H19", "F20",
1318
"G19", "C22", "C20", "D22", "D21", "F19", "F18", "D20", "D19"],
@@ -18,7 +23,6 @@ def add_vec(signal, pins, iostandard="LVCMOS33", extra=""):
1823
add(norflash0.oe_n, "M22", extra="SLEW = FAST | DRIVE = 8")
1924
add(norflash0.we_n, "N20", extra="SLEW = FAST | DRIVE = 8")
2025
add(norflash0.ce_n, "M21", extra="SLEW = FAST | DRIVE = 8")
21-
add(norflash0.rst_n, "P22", extra="SLEW = FAST | DRIVE = 8")
2226

2327
add(uart0.tx, "L17", extra="SLEW = SLOW")
2428
add(uart0.rx, "K18", extra="PULLUP")
@@ -38,8 +42,6 @@ def add_vec(signal, pins, iostandard="LVCMOS33", extra=""):
3842
NET "sys_clk" LOC = AB11 | IOSTANDARD = LVCMOS33;
3943
NET "sys_clk" TNM_NET = "GRPclk50";
4044
TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%;
41-
42-
NET "sys_rst" LOC = AA4 | IOSTANDARD = LVCMOS33;
4345
"""
4446

4547
return r

‎milkymist/m1reset/__init__.py

+23
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,23 @@
1+
from functools import partial
2+
3+
from migen.fhdl.structure import *
4+
5+
class Inst:
6+
def __init__(self):
7+
d = partial(declare_signal, self)
8+
d("trigger_reset")
9+
d("sys_rst")
10+
d("ac97_rst_n")
11+
d("videoin_rst_n")
12+
d("flash_rst_n")
13+
self._inst = Instance("m1reset",
14+
[("sys_rst", self.sys_rst),
15+
("ac97_rst_n", self.ac97_rst_n),
16+
("videoin_rst_n", self.videoin_rst_n),
17+
("flash_rst_n", self.flash_rst_n)],
18+
[("trigger_reset", self.trigger_reset)],
19+
clkport="sys_clk")
20+
21+
def get_fragment(self):
22+
return Fragment(instances=[self._inst],
23+
pads={self.ac97_rst_n, self.videoin_rst_n, self.flash_rst_n})

‎milkymist/norflash/__init__.py

+2-3
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,6 @@ def __init__(self, adr_width, rd_timing):
1313
d("oe_n")
1414
d("we_n")
1515
d("ce_n")
16-
d("rst_n")
1716
self.timeline = timeline.Inst(self.bus.cyc_i & self.bus.stb_i,
1817
[(0, [self.adr.eq(Cat(0, self.bus.adr_i[2:adr_width]))]),
1918
(rd_timing, [
@@ -27,6 +26,6 @@ def __init__(self, adr_width, rd_timing):
2726

2827
def get_fragment(self):
2928
comb = [self.oe_n.eq(0), self.we_n.eq(1),
30-
self.ce_n.eq(0), self.rst_n.eq(1)]
31-
return Fragment(comb, pads={self.adr, self.d, self.oe_n, self.we_n, self.ce_n, self.rst_n}) \
29+
self.ce_n.eq(0)]
30+
return Fragment(comb, pads={self.adr, self.d, self.oe_n, self.we_n, self.ce_n}) \
3231
+ self.timeline.get_fragment()

‎top.py

+9-4
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,13 @@
1+
from migen.fhdl.structure import *
12
from migen.fhdl import convtools, verilog, autofragment
23
from migen.bus import wishbone, csr, wishbone2csr
34

4-
from milkymist import lm32, norflash, uart
5+
from milkymist import m1reset, lm32, norflash, uart
56
import constraints
67

78
def get():
9+
reset0 = m1reset.Inst()
10+
811
cpu0 = lm32.Inst()
912
norflash0 = norflash.Inst(25, 12)
1013
wishbone2csr0 = wishbone2csr.Inst()
@@ -16,8 +19,10 @@ def get():
1619
uart0 = uart.Inst(0, 50*1000*1000, baud=115200)
1720
csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bus])
1821

19-
frag = autofragment.from_local()
22+
frag = autofragment.from_local() + Fragment(pads={reset0.trigger_reset})
2023
vns = convtools.Namespace()
21-
src_verilog = verilog.Convert(frag, name="soc", ns=vns)
22-
src_ucf = constraints.get(vns, norflash0, uart0)
24+
src_verilog = verilog.Convert(frag, name="soc",
25+
rst_signal=reset0.sys_rst,
26+
ns=vns)
27+
src_ucf = constraints.get(vns, reset0, norflash0, uart0)
2328
return (src_verilog, src_ucf)

‎verilog/m1reset/m1reset.v

+62
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,62 @@
1+
/*
2+
* Milkymist-NG SoC
3+
* Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
4+
*
5+
* This program is free software: you can redistribute it and/or modify
6+
* it under the terms of the GNU General Public License as published by
7+
* the Free Software Foundation, version 3 of the License.
8+
*
9+
* This program is distributed in the hope that it will be useful,
10+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
11+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12+
* GNU General Public License for more details.
13+
*
14+
* You should have received a copy of the GNU General Public License
15+
* along with this program. If not, see <http://www.gnu.org/licenses/>.
16+
*/
17+
18+
module m1reset(
19+
input sys_clk,
20+
input trigger_reset,
21+
22+
output reg sys_rst,
23+
output ac97_rst_n,
24+
output videoin_rst_n,
25+
output flash_rst_n
26+
);
27+
28+
reg [19:0] rst_debounce;
29+
initial rst_debounce <= 20'hFFFFF;
30+
initial sys_rst <= 1'b1;
31+
always @(posedge sys_clk) begin
32+
if(trigger_reset)
33+
rst_debounce <= 20'hFFFFF;
34+
else if(rst_debounce != 20'd0)
35+
rst_debounce <= rst_debounce - 20'd1;
36+
sys_rst <= rst_debounce != 20'd0;
37+
end
38+
39+
assign ac97_rst_n = ~sys_rst;
40+
assign videoin_rst_n = ~sys_rst;
41+
42+
/*
43+
* We must release the Flash reset before the system reset
44+
* because the Flash needs some time to come out of reset
45+
* and the CPU begins fetching instructions from it
46+
* as soon as the system reset is released.
47+
* From datasheet, minimum reset pulse width is 100ns
48+
* and reset-to-read time is 150ns.
49+
*/
50+
51+
reg [7:0] flash_rstcounter;
52+
initial flash_rstcounter <= 8'd0;
53+
always @(posedge sys_clk) begin
54+
if(trigger_reset)
55+
flash_rstcounter <= 8'd0;
56+
else if(~flash_rstcounter[7])
57+
flash_rstcounter <= flash_rstcounter + 8'd1;
58+
end
59+
60+
assign flash_rst_n = flash_rstcounter[7];
61+
62+
endmodule

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