Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: m-labs/migen
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: fdf022a04b44
Choose a base ref
...
head repository: m-labs/migen
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: 6f9f08f6eb39
Choose a head ref
  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Aug 12, 2013

  1. add += operator to fragment

    Nina Engelhardt authored and Sebastien Bourdeauducq committed Aug 12, 2013
    Copy the full SHA
    e12187a View commit details
  2. add ternary operator sel ? a : b

    Nina Engelhardt authored and Sebastien Bourdeauducq committed Aug 12, 2013
    Copy the full SHA
    6f9f08f View commit details
Showing with 26 additions and 0 deletions.
  1. +16 −0 migen/fhdl/structure.py
  2. +10 −0 migen/fhdl/verilog.py
16 changes: 16 additions & 0 deletions migen/fhdl/structure.py
Original file line number Diff line number Diff line change
@@ -94,6 +94,9 @@ def __init__(self, op, operands):
self.op = op
self.operands = operands

def Mux(sel, val1, val0):
return _Operator("m", [sel, val1, val0])

class _Slice(Value):
def __init__(self, value, start, stop):
Value.__init__(self)
@@ -275,3 +278,16 @@ def __add__(self, other):
self.specials | other.specials,
self.clock_domains + other.clock_domains,
self.sim + other.sim)

def __iadd__(self, other):
newsync = defaultdict(list)
for k, v in self.sync.items():
newsync[k] = v[:]
for k, v in other.sync.items():
newsync[k].extend(v)
self.comb += other.comb
self.sync = newsync
self.specials |= other.specials
self.clock_domains += other.clock_domains
self.sim += other.sim
return self
10 changes: 10 additions & 0 deletions migen/fhdl/verilog.py
Original file line number Diff line number Diff line change
@@ -58,6 +58,16 @@ def _printexpr(ns, node):
r2 = "$signed({1'd0, " + r2 + "})"
r = r1 + " " + node.op + " " + r2
s = s1 or s2
elif arity == 3:
assert node.op == "m"
r2, s2 = _printexpr(ns, node.operands[1])
r3, s3 = _printexpr(ns, node.operands[2])
if s2 and not s3:
r3 = "$signed({1'd0, " + r3 + "})"
if s3 and not s2:
r2 = "$signed({1'd0, " + r2 + "})"
r = r1 + " ? " + r2 + " : " + r3
s = s2 or s3
else:
raise TypeError
return "(" + r + ")", s