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base repository: m-labs/misoc
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  • 2 commits
  • 5 files changed
  • 1 contributor

Commits on Apr 25, 2013

  1. minimac3: move psync

    Sebastien Bourdeauducq committed Apr 25, 2013
    Copy the full SHA
    d64b645 View commit details
  2. Use the Migen asynchronous FIFO

    Sebastien Bourdeauducq committed Apr 25, 2013
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    4ff1175 View commit details
Showing with 9 additions and 162 deletions.
  1. +1 −5 build.py
  2. +8 −25 milkymist/framebuffer/__init__.py
  3. +0 −103 verilog/generic/asfifo.v
  4. +0 −29 verilog/generic/asfifo_graycounter.v
  5. 0 verilog/{generic → minimac3}/psync.v
6 changes: 1 addition & 5 deletions build.py
Original file line number Diff line number Diff line change
@@ -27,10 +27,6 @@ def main():
TIMESPEC "TSphy_tx_clk_io" = FROM "GRPphy_tx_clk" TO "PADS" 10 ns;
TIMESPEC "TSphy_rx_clk_io" = FROM "PADS" TO "GRPphy_rx_clk" 10 ns;
NET "asfifo*/counter_read/gray_count*" TIG;
NET "asfifo*/counter_write/gray_count*" TIG;
NET "asfifo*/preset_empty*" TIG;
NET "{dviclk0}" TNM_NET = "GRPdviclk0";
NET "{dviclk0}" CLOCK_DEDICATED_ROUTE = FALSE;
TIMESPEC "TSdviclk0" = PERIOD "GRPdviclk0" 26.7 ns HIGH 50%;
@@ -44,7 +40,7 @@ def main():
dviclk0=platform.lookup_request("dvi_in", 0).clk,
dviclk1=platform.lookup_request("dvi_in", 1).clk)

for d in ["generic", "m1crg", "s6ddrphy", "minimac3"]:
for d in ["m1crg", "s6ddrphy", "minimac3"]:
platform.add_source_dir(os.path.join("verilog", d))
platform.add_sources(os.path.join("verilog", "lm32", "submodule", "rtl"),
"lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
33 changes: 8 additions & 25 deletions milkymist/framebuffer/__init__.py
Original file line number Diff line number Diff line change
@@ -2,6 +2,7 @@
from migen.fhdl.specials import Instance
from migen.fhdl.module import Module
from migen.genlib.record import Record
from migen.genlib.fifo import AsyncFIFO
from migen.flow.actor import *
from migen.flow.network import *
from migen.flow.transactions import *
@@ -132,33 +133,15 @@ def __init__(self):
###

data_width = 2+2*3*_bpc_dac
fifo_full = Signal()
fifo_write_en = Signal()
fifo_read_en = Signal()
fifo_data_out = Signal(data_width)
fifo_data_in = Signal(data_width)
self.specials += Instance("asfifo",
Instance.Parameter("data_width", data_width),
Instance.Parameter("address_width", 8),

Instance.Output("data_out", fifo_data_out),
Instance.Output("empty"),
Instance.Input("read_en", fifo_read_en),
Instance.Input("clk_read", ClockSignal("vga")),

Instance.Input("data_in", fifo_data_in),
Instance.Output("full", fifo_full),
Instance.Input("write_en", fifo_write_en),
Instance.Input("clk_write", ClockSignal()),

Instance.Input("rst", 0))
fifo = AsyncFIFO(data_width, 256)
self.add_submodule(fifo, {"write": "sys", "read": "vga"})
fifo_in = self.dac.payload
fifo_out = Record(_dac_layout)
self.comb += [
self.dac.ack.eq(~fifo_full),
fifo_write_en.eq(self.dac.stb),
fifo_data_in.eq(fifo_in.raw_bits()),
fifo_out.raw_bits().eq(fifo_data_out),
self.dac.ack.eq(fifo.writable),
fifo.we.eq(self.dac.stb),
fifo.din.eq(fifo_in.raw_bits()),
fifo_out.raw_bits().eq(fifo.dout),
self.busy.eq(0)
]

@@ -177,7 +160,7 @@ def __init__(self):
self.vga_b.eq(fifo_out.p0.b)
)
]
self.comb += fifo_read_en.eq(pix_parity)
self.comb += fifo.re.eq(pix_parity)

def sim_fifo_gen():
while True:
103 changes: 0 additions & 103 deletions verilog/generic/asfifo.v

This file was deleted.

29 changes: 0 additions & 29 deletions verilog/generic/asfifo_graycounter.v

This file was deleted.

File renamed without changes.