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Commit 515cdb2

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author
Sebastien Bourdeauducq
committedMar 21, 2013
dvisampler: character synchronization
·
0.120.1
1 parent 7c4ca4f commit 515cdb2

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4 files changed

+78
-15
lines changed

4 files changed

+78
-15
lines changed
 

‎milkymist/dvisampler/__init__.py

+10-4
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,7 @@
55
from milkymist.dvisampler.edid import EDID
66
from milkymist.dvisampler.clocking import Clocking
77
from milkymist.dvisampler.datacapture import DataCapture
8+
from milkymist.dvisampler.charsync import CharSync
89

910
class DVISampler(Module, AutoReg):
1011
def __init__(self, inversions=""):
@@ -18,13 +19,18 @@ def __init__(self, inversions=""):
1819
for datan in "012":
1920
name = "data" + str(datan)
2021
invert = datan in inversions
22+
23+
signame = name + "_n" if invert else name
24+
s = Signal(name=signame)
25+
setattr(self, signame, s)
26+
2127
cap = DataCapture(8, invert)
2228
setattr(self.submodules, name + "_cap", cap)
23-
if invert:
24-
name += "_n"
25-
s = Signal(name=name)
26-
setattr(self, name, s)
2729
self.comb += [
2830
cap.pad.eq(s),
2931
cap.serdesstrobe.eq(self.clocking.serdesstrobe)
3032
]
33+
34+
charsync = CharSync()
35+
setattr(self.submodules, name + "_charsync", charsync)
36+
self.comb += charsync.raw_data.eq(cap.d)

‎milkymist/dvisampler/charsync.py

+51
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,51 @@
1+
from migen.fhdl.structure import *
2+
from migen.fhdl.module import Module
3+
from migen.genlib.cdc import MultiReg
4+
from migen.genlib.misc import optree
5+
from migen.bank.description import *
6+
7+
_control_tokens = [0b1101010100, 0b0010101011, 0b0101010100, 0b1010101011]
8+
9+
class CharSync(Module, AutoReg):
10+
def __init__(self, required_controls=8):
11+
self.raw_data = Signal(10)
12+
self.char_synced = Signal()
13+
self.data = Signal(10)
14+
15+
self._r_char_synced = RegisterField(1, READ_ONLY, WRITE_ONLY)
16+
17+
###
18+
19+
raw_data1 = Signal(10)
20+
self.sync.pix += raw_data1.eq(self.raw_data)
21+
raw = Signal(20)
22+
self.comb += raw.eq(Cat(raw_data1, self.raw_data))
23+
24+
found_control = Signal()
25+
control_position = Signal(max=10)
26+
for i in range(10):
27+
self.sync.pix += If(optree("|", [raw[i:i+10] == t for t in _control_tokens]),
28+
found_control.eq(1),
29+
control_position.eq(i)
30+
)
31+
32+
control_counter = Signal(max=required_controls)
33+
previous_control_position = Signal(max=10)
34+
word_sel = Signal(max=10)
35+
self.sync.pix += [
36+
If(found_control & (control_position == previous_control_position),
37+
If(control_counter == (required_controls - 1),
38+
control_counter.eq(0),
39+
self.char_synced.eq(1),
40+
word_sel.eq(control_position)
41+
).Else(
42+
control_counter.eq(control_counter + 1)
43+
)
44+
).Else(
45+
control_counter.eq(0)
46+
),
47+
previous_control_position.eq(control_position)
48+
]
49+
self.specials += MultiReg(self.char_synced, self._r_char_synced.field.w)
50+
51+
self.sync.pix += self.data.eq(raw >> word_sel)

‎software/include/hw/dvisampler.h

+13-10
Original file line numberDiff line numberDiff line change
@@ -13,16 +13,19 @@
1313
#define CSR_DVISAMPLER0_D0_DELAY_BUSY DVISAMPLER0_CSR(0x0C)
1414
#define CSR_DVISAMPLER0_D0_PHASE DVISAMPLER0_CSR(0x10)
1515
#define CSR_DVISAMPLER0_D0_PHASE_RESET DVISAMPLER0_CSR(0x14)
16-
17-
#define CSR_DVISAMPLER0_D1_DELAY_CTL DVISAMPLER0_CSR(0x18)
18-
#define CSR_DVISAMPLER0_D1_DELAY_BUSY DVISAMPLER0_CSR(0x1C)
19-
#define CSR_DVISAMPLER0_D1_PHASE DVISAMPLER0_CSR(0x20)
20-
#define CSR_DVISAMPLER0_D1_PHASE_RESET DVISAMPLER0_CSR(0x24)
21-
22-
#define CSR_DVISAMPLER0_D2_DELAY_CTL DVISAMPLER0_CSR(0x28)
23-
#define CSR_DVISAMPLER0_D2_DELAY_BUSY DVISAMPLER0_CSR(0x2C)
24-
#define CSR_DVISAMPLER0_D2_PHASE DVISAMPLER0_CSR(0x30)
25-
#define CSR_DVISAMPLER0_D2_PHASE_RESET DVISAMPLER0_CSR(0x34)
16+
#define CSR_DVISAMPLER0_D0_CHAR_SYNCED DVISAMPLER0_CSR(0x18)
17+
18+
#define CSR_DVISAMPLER0_D1_DELAY_CTL DVISAMPLER0_CSR(0x1C)
19+
#define CSR_DVISAMPLER0_D1_DELAY_BUSY DVISAMPLER0_CSR(0x20)
20+
#define CSR_DVISAMPLER0_D1_PHASE DVISAMPLER0_CSR(0x24)
21+
#define CSR_DVISAMPLER0_D1_PHASE_RESET DVISAMPLER0_CSR(0x28)
22+
#define CSR_DVISAMPLER0_D1_CHAR_SYNCED DVISAMPLER0_CSR(0x2C)
23+
24+
#define CSR_DVISAMPLER0_D2_DELAY_CTL DVISAMPLER0_CSR(0x30)
25+
#define CSR_DVISAMPLER0_D2_DELAY_BUSY DVISAMPLER0_CSR(0x34)
26+
#define CSR_DVISAMPLER0_D2_PHASE DVISAMPLER0_CSR(0x38)
27+
#define CSR_DVISAMPLER0_D2_PHASE_RESET DVISAMPLER0_CSR(0x3C)
28+
#define CSR_DVISAMPLER0_D2_CHAR_SYNCED DVISAMPLER0_CSR(0x40)
2629

2730
#define DVISAMPLER_DELAY_CAL 0x01
2831
#define DVISAMPLER_DELAY_RST 0x02

‎software/videomixer/main.c

+4-1
Original file line numberDiff line numberDiff line change
@@ -60,7 +60,10 @@ static void adjust_phase(void)
6060
CSR_DVISAMPLER0_D2_PHASE_RESET = 1;
6161
break;
6262
}
63-
//printf("Ph: %4d %4d %4d\n", d0, d1, d2);
63+
printf("Ph: %4d %4d %4d // %d%d%d\n", d0, d1, d2,
64+
CSR_DVISAMPLER0_D0_CHAR_SYNCED,
65+
CSR_DVISAMPLER0_D1_CHAR_SYNCED,
66+
CSR_DVISAMPLER0_D2_CHAR_SYNCED);
6467
}
6568

6669
static void vmix(void)

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