Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: m-labs/misoc
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: 4ff1175dcf50
Choose a base ref
...
head repository: m-labs/misoc
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: 43ac5c847124
Choose a head ref
  • 2 commits
  • 3 files changed
  • 1 contributor

Commits on Apr 25, 2013

  1. Tell the Xilinx crapware that DCM_CLKGEN does not phase align, as som…

    …e (but not all) of the ISE tools remark.
    Sebastien Bourdeauducq committed Apr 25, 2013
    Copy the full SHA
    de76faf View commit details
  2. Remove undriven reset signals

    Sebastien Bourdeauducq committed Apr 25, 2013
    Copy the full SHA
    43ac5c8 View commit details
Showing with 8 additions and 3 deletions.
  1. +5 −0 build.py
  2. +2 −2 milkymist/dvisampler/clocking.py
  3. +1 −1 milkymist/m1crg/__init__.py
5 changes: 5 additions & 0 deletions build.py
Original file line number Diff line number Diff line change
@@ -20,6 +20,11 @@ def main():
PIN "m1crg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
NET "vga_clk" TNM_NET = "GRPvga_clk";
NET "sys_clk" TNM_NET = "GRPsys_clk";
TIMESPEC "TSise_sucks1" = FROM "GRPvga_clk" TO "GRPsys_clk" TIG;
TIMESPEC "TSise_sucks2" = FROM "GRPsys_clk" TO "GRPvga_clk" TIG;
NET "{phy_rx_clk}" TNM_NET = "GRPphy_rx_clk";
NET "{phy_tx_clk}" TNM_NET = "GRPphy_tx_clk";
TIMESPEC "TSphy_rx_clk" = PERIOD "GRPphy_rx_clk" 40 ns HIGH 50%;
4 changes: 2 additions & 2 deletions milkymist/dvisampler/clocking.py
Original file line number Diff line number Diff line change
@@ -13,8 +13,8 @@ def __init__(self, pads):
self.serdesstrobe = Signal()
self.clock_domains._cd_pix = ClockDomain()
self.clock_domains._cd_pix5x = ClockDomain()
self.clock_domains._cd_pix10x = ClockDomain()
self.clock_domains._cd_pix20x = ClockDomain()
self.clock_domains._cd_pix10x = ClockDomain(reset_less=True)
self.clock_domains._cd_pix20x = ClockDomain(reset_less=True)

###

2 changes: 1 addition & 1 deletion milkymist/m1crg/__init__.py
Original file line number Diff line number Diff line change
@@ -13,7 +13,7 @@ def __init__(self, pads, outfreq1x):
self.clock_domains.cd_sys4x_rd = ClockDomain()
self.clock_domains.cd_eth_rx = ClockDomain()
self.clock_domains.cd_eth_tx = ClockDomain()
self.clock_domains.cd_vga = ClockDomain()
self.clock_domains.cd_vga = ClockDomain(reset_less=True)

self.clk4x_wr_strb = Signal()
self.clk4x_rd_strb = Signal()