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enjoy-digitalsbourdeauducq
enjoy-digital
authored and
sbourdeauducq
committedOct 17, 2014
remove trailing whitespaces
·
0.120.1
1 parent 20528c6 commit 34ed315

21 files changed

+95
-95
lines changed
 

‎make.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@ def _get_args():
4242
parser.add_argument("-Op", "--platform-option", default=[], nargs=2, action="append", help="set platform-specific option")
4343
parser.add_argument("-X", "--external", default="", help="use external directory for targets, platforms and imports")
4444
parser.add_argument("--csr_csv", default="csr.csv", help="CSV file to save the CSR map into")
45-
45+
4646
parser.add_argument("-d", "--decorate", default=[], action="append", help="apply simplification decorator to top-level")
4747
parser.add_argument("-Ob", "--build-option", default=[], nargs=2, action="append", help="set build option")
4848
parser.add_argument("-f", "--flash-proxy-dir", default=None, help="set search directory for flash proxy bitstreams")

‎misoclib/dfii/__init__.py

+5-5
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ def __init__(self, phase):
1010
self._baddress = CSRStorage(flen(phase.bank))
1111
self._wrdata = CSRStorage(flen(phase.wrdata))
1212
self._rddata = CSRStatus(flen(phase.rddata))
13-
13+
1414
###
1515

1616
self.comb += [
@@ -39,14 +39,14 @@ def __init__(self, a, ba, d, nphases=1):
3939
inti = dfi.Interface(a, ba, d, nphases)
4040
self.slave = dfi.Interface(a, ba, d, nphases)
4141
self.master = dfi.Interface(a, ba, d, nphases)
42-
42+
4343
self._control = CSRStorage(4) # sel, cke, odt, reset_n
44-
44+
4545
for n, phase in enumerate(inti.phases):
4646
setattr(self.submodules, "pi" + str(n), PhaseInjector(phase))
47-
47+
4848
###
49-
49+
5050
self.comb += If(self._control.storage[0],
5151
self.slave.connect(self.master)
5252
).Else(

‎misoclib/framebuffer/__init__.py

+2-2
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@
1010
class Framebuffer(Module, AutoCSR):
1111
def __init__(self, pads_vga, pads_dvi, lasmim):
1212
pack_factor = lasmim.dw//bpp
13-
13+
1414
g = DataFlowGraph()
1515

1616
self.fi = FrameInitiator(lasmim.aw, pack_factor)
@@ -23,7 +23,7 @@ def __init__(self, pads_vga, pads_dvi, lasmim):
2323
cast = structuring.Cast(lasmim.dw, pixel_layout(pack_factor), reverse_to=True)
2424
vtg = VTG(pack_factor)
2525
self.driver = Driver(pack_factor, pads_vga, pads_dvi)
26-
26+
2727
g.add_connection(self.fi, vtg, source_subr=self.fi.timing_subr, sink_ep="timing")
2828
g.add_connection(dma_out, cast)
2929
g.add_connection(cast, vtg, sink_ep="pixels")

‎misoclib/framebuffer/dvi.py

+4-4
Original file line numberDiff line numberDiff line change
@@ -27,9 +27,9 @@ def __init__(self):
2727
self.comb += q_m8_n.eq((n1d > 4) | ((n1d == 4) & ~d[0]))
2828
for i in range(8):
2929
if i:
30-
curval = curval ^ d[i] ^ q_m8_n
30+
curval = curval ^ d[i] ^ q_m8_n
3131
else:
32-
curval = d[0]
32+
curval = d[0]
3333
self.sync += q_m[i].eq(curval)
3434
self.sync += q_m[8].eq(~q_m8_n)
3535

@@ -199,15 +199,15 @@ def _decode_tmds(b):
199199
if __name__ == "__main__":
200200
from migen.sim.generic import run_simulation
201201
from random import Random
202-
202+
203203
rng = Random(788)
204204
test_list = [rng.randrange(256) for i in range(500)]
205205
tb = _EncoderTB(test_list)
206206
run_simulation(tb)
207207

208208
check = [_decode_tmds(out)[3] for out in tb.outs]
209209
assert(check == test_list)
210-
210+
211211
nb0 = 0
212212
nb1 = 0
213213
for out in tb.outs:

‎misoclib/framebuffer/format.py

+5-5
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,7 @@ def __init__(self, bus_aw, pack_factor, ndmas=1):
4141
("hsync_start", hbits_dyn, 656, h_alignment_bits),
4242
("hsync_end", hbits_dyn, 752, h_alignment_bits),
4343
("hscan", hbits_dyn, 800, h_alignment_bits),
44-
44+
4545
("vres", _vbits, 480),
4646
("vsync_start", _vbits, 492),
4747
("vsync_end", _vbits, 494),
@@ -81,10 +81,10 @@ def __init__(self, pack_factor):
8181
hactive = Signal()
8282
vactive = Signal()
8383
active = Signal()
84-
84+
8585
hcounter = Signal(hbits_dyn)
8686
vcounter = Signal(_vbits)
87-
87+
8888
skip = bpc - bpc_phy
8989
self.comb += [
9090
active.eq(hactive & vactive),
@@ -106,7 +106,7 @@ def __init__(self, pack_factor):
106106
generate_frame_done.eq(0),
107107
If(generate_en,
108108
hcounter.eq(hcounter + 1),
109-
109+
110110
If(hcounter == 0, hactive.eq(1)),
111111
If(hcounter == tr.hres, hactive.eq(0)),
112112
If(hcounter == tr.hsync_start, self.phy.payload.hsync.eq(1)),
@@ -120,7 +120,7 @@ def __init__(self, pack_factor):
120120
vcounter.eq(vcounter + 1)
121121
)
122122
),
123-
123+
124124
If(vcounter == 0, vactive.eq(1)),
125125
If(vcounter == tr.vres, vactive.eq(0)),
126126
If(vcounter == tr.vsync_start, self.phy.payload.vsync.eq(1)),

‎misoclib/framebuffer/phy.py

+5-5
Original file line numberDiff line numberDiff line change
@@ -11,14 +11,14 @@ class _FIFO(Module):
1111
def __init__(self, pack_factor):
1212
self.phy = Sink(phy_layout(pack_factor))
1313
self.busy = Signal()
14-
14+
1515
self.pix_hsync = Signal()
1616
self.pix_vsync = Signal()
1717
self.pix_de = Signal()
1818
self.pix_r = Signal(bpc_phy)
1919
self.pix_g = Signal(bpc_phy)
2020
self.pix_b = Signal(bpc_phy)
21-
21+
2222
###
2323

2424
fifo = RenameClockDomains(AsyncFIFO(phy_layout(pack_factor), 512),
@@ -81,7 +81,7 @@ def __init__(self, pads_vga, pads_dvi):
8181
self.specials += Instance("DCM_CLKGEN",
8282
p_CLKFXDV_DIVIDE=2, p_CLKFX_DIVIDE=4, p_CLKFX_MD_MAX=1.0, p_CLKFX_MULTIPLY=2,
8383
p_CLKIN_PERIOD=20.0, p_SPREAD_SPECTRUM="NONE", p_STARTUP_WAIT="FALSE",
84-
84+
8585
i_CLKIN=ClockSignal("base50"), o_CLKFX=clk_pix_unbuffered,
8686
i_PROGCLK=ClockSignal(), i_PROGDATA=pix_progdata, i_PROGEN=pix_progen,
8787
o_PROGDONE=pix_progdone, o_LOCKED=pix_locked,
@@ -145,12 +145,12 @@ def __init__(self, pads_vga, pads_dvi):
145145
p_CLKOUT1_DIVIDE=5, # pix2x
146146
p_CLKOUT2_DIVIDE=10, # pix
147147
p_COMPENSATION="INTERNAL",
148-
148+
149149
i_CLKINSEL=1,
150150
i_CLKIN1=clk_pix_unbuffered,
151151
o_CLKOUT0=pll_clk0, o_CLKOUT1=pll_clk1, o_CLKOUT2=pll_clk2,
152152
o_CLKFBOUT=clkfbout, i_CLKFBIN=clkfbout,
153-
o_LOCKED=pll_locked,
153+
o_LOCKED=pll_locked,
154154
i_RST=~pix_locked | self._r_pll_reset.storage,
155155

156156
i_DADDR=self._r_pll_adr.storage,

‎misoclib/gensoc/__init__.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,7 @@ def __init__(self, platform, clk_freq, cpu_reset_address, sram_size=4096, l2_siz
6969

7070
# add CPU Verilog sources
7171
if cpu_type == "lm32":
72-
platform.add_sources(os.path.join("verilog", "lm32", "submodule", "rtl"),
72+
platform.add_sources(os.path.join("verilog", "lm32", "submodule", "rtl"),
7373
"lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
7474
"lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
7575
"lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",

‎misoclib/identifier/__init__.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@ def __init__(self, sysid, frequency, l2_size, revision=None):
99
self._r_revision = CSRStatus(32)
1010
self._r_frequency = CSRStatus(32)
1111
self._r_l2_size = CSRStatus(8)
12-
12+
1313
###
1414

1515
if revision is None:

‎misoclib/lasmicon/__init__.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,7 @@ def __init__(self, phy_settings, geom_settings, timing_settings):
3838
read_latency=phy_settings.read_latency+1,
3939
write_latency=phy_settings.write_latency+1)
4040
self.nrowbits = geom_settings.col_a - address_align
41-
41+
4242
###
4343

4444
self.submodules.refresher = Refresher(geom_settings.mux_a, geom_settings.bank_a,

‎misoclib/lasmicon/bankmachine.py

+7-7
Original file line numberDiff line numberDiff line change
@@ -10,21 +10,21 @@ class _AddressSlicer:
1010
def __init__(self, col_a, address_align):
1111
self.col_a = col_a
1212
self.address_align = address_align
13-
13+
1414
def row(self, address):
1515
split = self.col_a - self.address_align
1616
if isinstance(address, int):
1717
return address >> split
1818
else:
1919
return address[split:]
20-
20+
2121
def col(self, address):
2222
split = self.col_a - self.address_align
2323
if isinstance(address, int):
2424
return (address & (2**split - 1)) << self.address_align
2525
else:
2626
return Cat(Replicate(0, self.address_align), address[:split])
27-
27+
2828
class BankMachine(Module):
2929
def __init__(self, geom_settings, timing_settings, address_align, bankn, req):
3030
self.refresh_req = Signal()
@@ -47,7 +47,7 @@ def __init__(self, geom_settings, timing_settings, address_align, bankn, req):
4747
reqf = self.req_fifo.dout
4848

4949
slicer = _AddressSlicer(geom_settings.col_a, address_align)
50-
50+
5151
# Row tracking
5252
has_openrow = Signal()
5353
openrow = Signal(geom_settings.row_a)
@@ -64,7 +64,7 @@ def __init__(self, geom_settings, timing_settings, address_align, bankn, req):
6464
has_openrow.eq(0)
6565
)
6666
]
67-
67+
6868
# Address generation
6969
s_row_adr = Signal()
7070
self.comb += [
@@ -75,7 +75,7 @@ def __init__(self, geom_settings, timing_settings, address_align, bankn, req):
7575
self.cmd.a.eq(slicer.col(reqf.adr))
7676
)
7777
]
78-
78+
7979
# Respect write-to-precharge specification
8080
precharge_ok = Signal()
8181
t_unsafe_precharge = 2 + timing_settings.tWR - 1
@@ -88,7 +88,7 @@ def __init__(self, geom_settings, timing_settings, address_align, bankn, req):
8888
unsafe_precharge_count.eq(unsafe_precharge_count-1)
8989
)
9090
]
91-
91+
9292
# Control and command generation FSM
9393
fsm = FSM()
9494
self.submodules += fsm

‎misoclib/lasmicon/multiplexer.py

+15-15
Original file line numberDiff line numberDiff line change
@@ -30,15 +30,15 @@ def __init__(self, requests):
3030
self.want_cmds = Signal()
3131
# NB: cas_n/ras_n/we_n are 1 when stb is inactive
3232
self.cmd = CommandRequestRW(flen(requests[0].a), flen(requests[0].ba))
33-
33+
3434
###
3535

3636
rr = RoundRobin(len(requests), SP_CE)
3737
self.submodules += rr
38-
38+
3939
self.comb += [rr.request[i].eq(req.stb & ((req.is_cmd & self.want_cmds) | ((req.is_read == self.want_reads) | (req.is_write == self.want_writes))))
4040
for i, req in enumerate(requests)]
41-
41+
4242
stb = Signal()
4343
self.comb += stb.eq(Array(req.stb for req in requests)[rr.grant])
4444
for name in ["a", "ba", "is_read", "is_write", "is_cmd"]:
@@ -51,7 +51,7 @@ def __init__(self, requests):
5151
self.comb += self.cmd.stb.eq(stb \
5252
& ((self.cmd.is_cmd & self.want_cmds) | ((self.cmd.is_read == self.want_reads) \
5353
& (self.cmd.is_write == self.want_writes))))
54-
54+
5555
self.comb += [If(self.cmd.stb & self.cmd.ack & (rr.grant == i), req.ack.eq(1))
5656
for i, req in enumerate(requests)]
5757
self.comb += rr.ce.eq(self.cmd.ack)
@@ -61,9 +61,9 @@ def __init__(self, commands, dfi):
6161
ncmd = len(commands)
6262
nph = len(dfi.phases)
6363
self.sel = [Signal(max=ncmd) for i in range(nph)]
64-
64+
6565
###
66-
66+
6767
def stb_and(cmd, attr):
6868
if not hasattr(cmd, "stb"):
6969
return 0
@@ -91,7 +91,7 @@ def stb_and(cmd, attr):
9191
class Multiplexer(Module, AutoCSR):
9292
def __init__(self, phy_settings, geom_settings, timing_settings, bank_machines, refresher, dfi, lasmic):
9393
assert(phy_settings.nphases == len(dfi.phases))
94-
94+
9595
# Command choosing
9696
requests = [bm.cmd for bm in bank_machines]
9797
choose_cmd = _CommandChooser(requests)
@@ -104,24 +104,24 @@ def __init__(self, phy_settings, geom_settings, timing_settings, bank_machines,
104104
self.comb += [
105105
choose_cmd.want_cmds.eq(1),
106106
choose_req.want_cmds.eq(1)
107-
]
107+
]
108108
self.submodules += choose_cmd, choose_req
109-
109+
110110
# Command steering
111111
nop = CommandRequest(geom_settings.mux_a, geom_settings.bank_a)
112112
commands = [nop, choose_cmd.cmd, choose_req.cmd, refresher.cmd] # nop must be 1st
113113
(STEER_NOP, STEER_CMD, STEER_REQ, STEER_REFRESH) = range(4)
114114
steerer = _Steerer(commands, dfi)
115115
self.submodules += steerer
116-
116+
117117
# Read/write turnaround
118118
read_available = Signal()
119119
write_available = Signal()
120120
self.comb += [
121121
read_available.eq(optree("|", [req.stb & req.is_read for req in requests])),
122122
write_available.eq(optree("|", [req.stb & req.is_write for req in requests]))
123123
]
124-
124+
125125
def anti_starvation(timeout):
126126
en = Signal()
127127
max_time = Signal()
@@ -139,12 +139,12 @@ def anti_starvation(timeout):
139139
return en, max_time
140140
read_time_en, max_read_time = anti_starvation(timing_settings.read_time)
141141
write_time_en, max_write_time = anti_starvation(timing_settings.write_time)
142-
142+
143143
# Refresh
144144
self.comb += [bm.refresh_req.eq(refresher.req) for bm in bank_machines]
145145
go_to_refresh = Signal()
146146
self.comb += go_to_refresh.eq(optree("&", [bm.refresh_gnt for bm in bank_machines]))
147-
147+
148148
# Datapath
149149
all_rddata = [p.rddata for p in dfi.phases]
150150
all_wrdata = [p.wrdata for p in dfi.phases]
@@ -154,11 +154,11 @@ def anti_starvation(timeout):
154154
Cat(*all_wrdata).eq(lasmic.dat_w),
155155
Cat(*all_wrdata_mask).eq(~lasmic.dat_we)
156156
]
157-
157+
158158
# Control FSM
159159
fsm = FSM()
160160
self.submodules += fsm
161-
161+
162162
def steerer_sel(steerer, phy_settings, r_w_n):
163163
r = []
164164
for i in range(phy_settings.nphases):

‎misoclib/lasmicon/refresher.py

+3-3
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@ def __init__(self, a, ba, tRP, tREFI, tRFC):
99
self.req = Signal()
1010
self.ack = Signal() # 1st command 1 cycle after assertion of ack
1111
self.cmd = CommandRequest(a, ba)
12-
12+
1313
###
1414

1515
# Refresh sequence generator:
@@ -37,7 +37,7 @@ def __init__(self, a, ba, tRP, tREFI, tRFC):
3737
seq_done.eq(1)
3838
])
3939
])
40-
40+
4141
# Periodic refresh counter
4242
counter = Signal(max=tREFI)
4343
start = Signal()
@@ -50,7 +50,7 @@ def __init__(self, a, ba, tRP, tREFI, tRFC):
5050
counter.eq(counter - 1)
5151
)
5252
]
53-
53+
5454
# Control FSM
5555
fsm = FSM()
5656
self.submodules += fsm

‎misoclib/lasmicon/test/common.py

+4-4
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ def ns(t, margin=True):
1616

1717
sdram_phy = lasmicon.PhySettings(
1818
memtype="DDR",
19-
dfi_d=64,
19+
dfi_d=64,
2020
nphases=2,
2121
rdphase=0,
2222
wrphase=1,
@@ -39,7 +39,7 @@ def ns(t, margin=True):
3939
tWTR=2,
4040
tREFI=ns(7800, False),
4141
tRFC=ns(70),
42-
42+
4343
req_queue_size=8,
4444
read_time=32,
4545
write_time=16
@@ -78,7 +78,7 @@ def __init__(self, cmd, rw=False):
7878
self.cmd = cmd
7979
if rw:
8080
self.comb += self.cmd.ack.eq(1)
81-
81+
8282
def do_simulation(self, selfp):
8383
elts = ["@" + str(selfp.simulator.cycle_counter)]
8484
cmdp = selfp.cmd
@@ -90,7 +90,7 @@ def do_simulation(self, selfp):
9090
class DFILogger(Module):
9191
def __init__(self, dfi):
9292
self.dfi = dfi
93-
93+
9494
def do_simulation(self, selfp):
9595
dfip = selfp.dfi
9696
for i, p in enumerate(dfip.phases):

‎misoclib/lasmicon/test/refresher.py

+3-3
Original file line numberDiff line numberDiff line change
@@ -13,10 +13,10 @@ def __init__(self, req, ack):
1313
self.ack = ack
1414
self.state = 0
1515
self.prng = Random(92837)
16-
16+
1717
def do_simulation(self, selfp):
1818
elts = ["@" + str(selfp.simulator.cycle_counter)]
19-
19+
2020
if self.state == 0:
2121
if selfp.req:
2222
elts.append("Refresher requested access")
@@ -31,7 +31,7 @@ def do_simulation(self, selfp):
3131
elts.append("Refresher released access")
3232
selfp.ack = 0
3333
self.state = 0
34-
34+
3535
if len(elts) > 1:
3636
print("\t".join(elts))
3737

‎misoclib/lm32/__init__.py

+3-3
Original file line numberDiff line numberDiff line change
@@ -16,9 +16,9 @@ def __init__(self, eba_reset):
1616

1717
i_clk_i=ClockSignal(),
1818
i_rst_i=ResetSignal(),
19-
19+
2020
i_interrupt=self.interrupt,
21-
21+
2222
o_I_ADR_O=i_adr_o,
2323
o_I_DAT_O=i.dat_w,
2424
o_I_SEL_O=i.sel,
@@ -31,7 +31,7 @@ def __init__(self, eba_reset):
3131
i_I_ACK_I=i.ack,
3232
i_I_ERR_I=i.err,
3333
i_I_RTY_I=0,
34-
34+
3535
o_D_ADR_O=d_adr_o,
3636
o_D_DAT_O=d.dat_w,
3737
o_D_SEL_O=d.sel,

‎misoclib/minimac3/__init__.py

+7-7
Original file line numberDiff line numberDiff line change
@@ -13,15 +13,15 @@ def __init__(self, pads):
1313
self._rx_count_1 = CSRStatus(_count_width)
1414
self._tx_count = CSRStorage(_count_width, write_from_dev=True)
1515
self._tx_start = CSR()
16-
16+
1717
self.submodules.ev = EventManager()
1818
self.ev.rx0 = EventSourcePulse()
1919
self.ev.rx1 = EventSourcePulse()
2020
self.ev.tx = EventSourcePulse()
2121
self.ev.finalize()
22-
22+
2323
self.membus = wishbone.Interface()
24-
24+
2525
###
2626

2727
init = Signal(reset=1)
@@ -34,10 +34,10 @@ def __init__(self, pads):
3434
rx_pending_1_r = Signal()
3535
self.comb += [
3636
pads.rst_n.eq(~self._phy_reset.storage),
37-
37+
3838
rx_ready_0.eq(init | (rx_pending_0_r & ~rx_pending_0)),
3939
rx_ready_1.eq(init | (rx_pending_1_r & ~rx_pending_1)),
40-
40+
4141
self._tx_count.dat_w.eq(0),
4242
self._tx_count.we.eq(self.ev.tx.trigger)
4343
]
@@ -59,7 +59,7 @@ def __init__(self, pads):
5959
Instance.Input("tx_start", self._tx_start.re),
6060
Instance.Input("tx_count", self._tx_count.storage),
6161
Instance.Output("tx_done", self.ev.tx.trigger),
62-
62+
6363
Instance.Input("wb_adr_i", self.membus.adr),
6464
Instance.Input("wb_dat_i", self.membus.dat_w),
6565
Instance.Input("wb_sel_i", self.membus.sel),
@@ -68,7 +68,7 @@ def __init__(self, pads):
6868
Instance.Input("wb_we_i", self.membus.we),
6969
Instance.Output("wb_dat_o", self.membus.dat_r),
7070
Instance.Output("wb_ack_o", self.membus.ack),
71-
71+
7272
Instance.Input("phy_tx_clk", ClockSignal("eth_tx")),
7373
Instance.Output("phy_tx_data", pads.tx_data),
7474
Instance.Output("phy_tx_en", pads.tx_en),

‎misoclib/mxcrg/__init__.py

+3-3
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ def __init__(self, pads, outfreq1x):
1616
self.clk4x_rd_strb = Signal()
1717

1818
###
19-
19+
2020
infreq = 50*1000000
2121
ratio = Fraction(outfreq1x)/Fraction(infreq)
2222
in_period = float(Fraction(1000000000)/Fraction(infreq))
@@ -27,10 +27,10 @@ def __init__(self, pads, outfreq1x):
2727
Instance.Parameter("f_div", ratio.denominator),
2828
Instance.Input("clk50_pad", pads.clk50),
2929
Instance.Input("trigger_reset", pads.trigger_reset),
30-
30+
3131
Instance.Input("eth_rx_clk_pad", pads.eth_rx_clk),
3232
Instance.Input("eth_tx_clk_pad", pads.eth_tx_clk),
33-
33+
3434
Instance.Output("sys_clk", self.cd_sys.clk),
3535
Instance.Output("sys_rst", self.cd_sys.rst),
3636
Instance.Output("clk2x_270", self.cd_sdram_half.clk),

‎misoclib/sdramphy/gensdrphy.py

+8-8
Original file line numberDiff line numberDiff line change
@@ -1,15 +1,15 @@
11
#
2-
# 1:1 frequency-ratio Generic SDR PHY
3-
#
4-
# The GENSDRPHY is validated on CycloneIV (Altera) but since it does
2+
# 1:1 frequency-ratio Generic SDR PHY
3+
#
4+
# The GENSDRPHY is validated on CycloneIV (Altera) but since it does
55
# not use vendor-dependent code, it can also be used on other architectures.
66
#
77
# The PHY needs 2 Clock domains:
88
# - sys_clk : The System Clock domain
9-
# - sys_clk_ps : The System Clock domain with its phase shifted
9+
# - sys_clk_ps : The System Clock domain with its phase shifted
1010
# (-3ns on C4@100MHz)
1111
#
12-
# Assert dfi_wrdata_en and present the data
12+
# Assert dfi_wrdata_en and present the data
1313
# on dfi_wrdata_mask/dfi_wrdata in the same
1414
# cycle as the write command.
1515
#
@@ -46,12 +46,12 @@ def __init__(self, pads):
4646
read_latency=4,
4747
write_latency=0
4848
)
49-
49+
5050
self.dfi = Interface(a, ba, d)
5151

5252
###
5353

54-
#
54+
#
5555
# Command/address
5656
#
5757
self.sync += [
@@ -82,7 +82,7 @@ def __init__(self, pads):
8282
self.sync.sys_ps += sd_dq_in_ps.eq(pads.dq)
8383
self.sync += self.dfi.p0.rddata.eq(sd_dq_in_ps)
8484

85-
#
85+
#
8686
# DQ/DM control
8787
#
8888
d_dfi_wrdata_en = Signal()

‎misoclib/sdramphy/initsequence.py

+4-4
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
def get_sdram_phy_header(sdram_phy):
44
r = "#ifndef __GENERATED_SDRAM_PHY_H\n#define __GENERATED_SDRAM_PHY_H\n"
55
r += "#include <hw/common.h>\n#include <generated/csr.h>\n#include <hw/flags.h>\n\n"
6-
6+
77
nphases = sdram_phy.phy_settings.nphases
88
r += "#define DFII_NPHASES "+str(nphases)+"\n\n"
99

@@ -29,7 +29,7 @@ def get_sdram_phy_header(sdram_phy):
2929
3030
#define command_prd(X) command_p{rdphase}(X)
3131
#define command_pwr(X) command_p{wrphase}(X)
32-
""".format(rdphase=str(sdram_phy.phy_settings.rdphase), wrphase=str(sdram_phy.phy_settings.wrphase))
32+
""".format(rdphase=str(sdram_phy.phy_settings.rdphase), wrphase=str(sdram_phy.phy_settings.wrphase))
3333
r +="\n"
3434

3535
#
@@ -65,7 +65,7 @@ def get_sdram_phy_header(sdram_phy):
6565
}
6666

6767
cl = sdram_phy.phy_settings.cl
68-
68+
6969
if sdram_phy.phy_settings.memtype == "SDR":
7070
bl = sdram_phy.phy_settings.nphases
7171
mr = log2_int(bl) + (cl << 4)
@@ -143,7 +143,7 @@ def get_sdram_phy_header(sdram_phy):
143143
bl = 2*sdram_phy.phy_settings.nphases
144144
if bl != 8:
145145
raise NotImplementedError("DDR3 PHY header generator only supports BL of 8")
146-
146+
147147
def format_mr0(cl, wr, dll_reset):
148148
cl_to_mr0 = {
149149
5 : 0b0010,

‎misoclib/sdramphy/s6ddrphy.py

+12-12
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,12 @@
11
# 1:2 frequency-ratio DDR / LPDDR / DDR2 PHY for Spartan-6
2-
#
3-
# Assert dfi_wrdata_en and present the data
2+
#
3+
# Assert dfi_wrdata_en and present the data
44
# on dfi_wrdata_mask/dfi_wrdata in the same
55
# cycle as the write command.
66
#
77
# Assert dfi_rddata_en in the same cycle as the read
88
# command. The data will come back on dfi_rddata
9-
# 5 cycles later, along with the assertion
9+
# 5 cycles later, along with the assertion
1010
# of dfi_rddata_valid.
1111
#
1212
# This PHY only supports CAS Latency 3.
@@ -60,7 +60,7 @@ def __init__(self, pads, memtype, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
6060
sdram_full_wr_clk = ClockSignal("sdram_full_wr")
6161
sdram_full_rd_clk = ClockSignal("sdram_full_rd")
6262

63-
#
63+
#
6464
# Command/address
6565
#
6666

@@ -104,7 +104,7 @@ def __init__(self, pads, memtype, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
104104
if hasattr(pads, "cs_n"):
105105
sd_sdram_half += pads.cs_n.eq(r_dfi[phase_sel].cs_n)
106106

107-
#
107+
#
108108
# Bitslip
109109
#
110110
bitslip_cnt = Signal(4)
@@ -119,7 +119,7 @@ def __init__(self, pads, memtype, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
119119
)
120120
]
121121

122-
#
122+
#
123123
# DQ/DQS/DM data
124124
#
125125
sdram_half_clk_n = Signal()
@@ -130,7 +130,7 @@ def __init__(self, pads, memtype, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
130130
dqs_t_d0 = Signal()
131131
dqs_t_d1 = Signal()
132132

133-
dqs_o = Signal(d//8)
133+
dqs_o = Signal(d//8)
134134
dqs_t = Signal(d//8)
135135

136136
self.comb += [
@@ -194,7 +194,7 @@ def __init__(self, pads, memtype, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
194194

195195
sd_sdram_half += postamble.eq(drive_dqs)
196196

197-
d_dfi = [Record(phase_wrdata_description(nphases*d)+phase_rddata_description(nphases*d))
197+
d_dfi = [Record(phase_wrdata_description(nphases*d)+phase_rddata_description(nphases*d))
198198
for i in range(2*nphases)]
199199

200200
for n, phase in enumerate(self.dfi.phases):
@@ -334,23 +334,23 @@ def __init__(self, pads, memtype, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
334334
if hasattr(pads, "odt"):
335335
self.comb += pads.odt.eq(0)
336336

337-
#
337+
#
338338
# DQ/DQS/DM control
339339
#
340340
self.comb += drive_dq.eq(d_dfi[self.phy_settings.wrphase].wrdata_en)
341341

342342
d_dfi_wrdata_en = Signal()
343343
sd_sys += d_dfi_wrdata_en.eq(d_dfi[self.phy_settings.wrphase].wrdata_en)
344-
344+
345345
r_dfi_wrdata_en = Signal(2)
346-
sd_sdram_half += r_dfi_wrdata_en.eq(Cat(d_dfi_wrdata_en, r_dfi_wrdata_en[0]))
346+
sd_sdram_half += r_dfi_wrdata_en.eq(Cat(d_dfi_wrdata_en, r_dfi_wrdata_en[0]))
347347

348348
self.comb += drive_dqs.eq(r_dfi_wrdata_en[1])
349349

350350
rddata_sr = Signal(self.phy_settings.read_latency)
351351
sd_sys += rddata_sr.eq(Cat(rddata_sr[1:self.phy_settings.read_latency],
352352
d_dfi[self.phy_settings.rdphase].rddata_en))
353-
353+
354354
for n, phase in enumerate(self.dfi.phases):
355355
self.comb += [
356356
phase.rddata.eq(d_dfi[n].rddata),

‎misoclib/timer/__init__.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@ def __init__(self, width=32):
99
self._en = CSRStorage()
1010
self._update_value = CSR()
1111
self._value = CSRStatus(width)
12-
12+
1313
self.submodules.ev = EventManager()
1414
self.ev.zero = EventSourceProcess()
1515
self.ev.finalize()

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