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asynchronous RTIO
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sbourdeauducq committed Nov 29, 2014
1 parent 9c41f98 commit 901073a
Showing 9 changed files with 222 additions and 113 deletions.
8 changes: 5 additions & 3 deletions artiq/coredevice/rtio.py
Original file line number Diff line number Diff line change
@@ -107,7 +107,8 @@ def sync(self):
the output of the DDS).
"""
syscall("rtio_sync", self.channel)
while syscall("rtio_get_counter") < self.previous_timestamp:
pass

@kernel
def on(self):
@@ -192,7 +193,7 @@ def count(self):
"""
count = 0
while syscall("rtio_get", self.channel) >= 0:
while syscall("rtio_get", self.channel, self.previous_timestamp) >= 0:
count += 1
return count

@@ -204,4 +205,5 @@ def timestamp(self):
If the gate is permanently closed, returns a negative value.
"""
return cycles_to_time(syscall("rtio_get", self.channel))
return cycles_to_time(syscall("rtio_get", self.channel,
self.previous_timestamp))
3 changes: 1 addition & 2 deletions artiq/coredevice/runtime.py
Original file line number Diff line number Diff line change
@@ -16,9 +16,8 @@
"rtio_oe": "ib:n",
"rtio_set": "Iii:n",
"rtio_replace": "Iii:n",
"rtio_sync": "i:n",
"rtio_get_counter": "n:I",
"rtio_get": "i:I",
"rtio_get": "iI:I",
"rtio_pileup_count": "i:i",
"dds_phase_clear_en": "ib:n",
"dds_program": "IiiiIbb:n",
267 changes: 195 additions & 72 deletions soc/artiqlib/rtio/core.py

Large diffs are not rendered by default.

10 changes: 5 additions & 5 deletions soc/artiqlib/rtio/phy.py
Original file line number Diff line number Diff line change
@@ -5,25 +5,25 @@


class SimplePHY(Module):
def __init__(self, pads, output_only_pads=set(), mini_pads=set()):
self.rbus = create_rbus(0, pads, output_only_pads, mini_pads)
def __init__(self, pads, output_only_pads=set()):
self.rbus = create_rbus(0, pads, output_only_pads)
self.loopback_latency = 3

# # #

for pad, chif in zip(pads, self.rbus):
o_pad = Signal()
self.sync += If(chif.o_stb, o_pad.eq(chif.o_value))
self.sync.rio += If(chif.o_stb, o_pad.eq(chif.o_value))
if hasattr(chif, "oe"):
ts = TSTriple()
i_pad = Signal()
self.sync += ts.oe.eq(chif.oe)
self.sync.rio += ts.oe.eq(chif.oe)
self.comb += ts.o.eq(o_pad)
self.specials += MultiReg(ts.i, i_pad), \
ts.get_tristate(pad)

i_pad_d = Signal()
self.sync += i_pad_d.eq(i_pad)
self.sync.rio += i_pad_d.eq(i_pad)
self.comb += chif.i_stb.eq(i_pad ^ i_pad_d), \
chif.i_value.eq(i_pad)
else:
8 changes: 3 additions & 5 deletions soc/artiqlib/rtio/rbus.py
Original file line number Diff line number Diff line change
@@ -2,7 +2,7 @@
from migen.genlib.record import Record


def create_rbus(fine_ts_bits, pads, output_only_pads, mini_pads):
def create_rbus(fine_ts_bits, pads, output_only_pads):
rbus = []
for pad in pads:
layout = [
@@ -11,7 +11,7 @@ def create_rbus(fine_ts_bits, pads, output_only_pads, mini_pads):
]
if fine_ts_bits:
layout.append(("o_fine_ts", fine_ts_bits))
if pad not in output_only_pads and pad not in mini_pads:
if pad not in output_only_pads:
layout += [
("oe", 1),
("i_stb", 1),
@@ -20,9 +20,7 @@ def create_rbus(fine_ts_bits, pads, output_only_pads, mini_pads):
]
if fine_ts_bits:
layout.append(("i_fine_ts", fine_ts_bits))
chif = Record(layout)
chif.mini = pad in mini_pads
rbus.append(chif)
rbus.append(Record(layout))
return rbus


30 changes: 9 additions & 21 deletions soc/runtime/rtio.c
Original file line number Diff line number Diff line change
@@ -8,10 +8,8 @@ long long int previous_fud_end_time;
void rtio_init(void)
{
previous_fud_end_time = 0;
rtio_reset_counter_write(1);
rtio_reset_logic_write(1);
rtio_reset_counter_write(0);
rtio_reset_logic_write(0);
rtio_reset_write(1);
rtio_reset_write(0);
}

void rtio_oe(int channel, int oe)
@@ -28,8 +26,7 @@ void rtio_set(long long int timestamp, int channel, int value)
while(!rtio_o_writable_read());
rtio_o_we_write(1);
if(rtio_o_underflow_read()) {
rtio_reset_logic_write(1);
rtio_reset_logic_write(0);
rtio_o_underflow_reset_write(1);
exception_raise(EID_RTIO_UNDERFLOW);
}
}
@@ -41,33 +38,25 @@ void rtio_replace(long long int timestamp, int channel, int value)
rtio_o_value_write(value);
rtio_o_replace_write(1);
if(rtio_o_underflow_read()) {
rtio_reset_logic_write(1);
rtio_reset_logic_write(0);
rtio_o_underflow_reset_write(1);
exception_raise(EID_RTIO_UNDERFLOW);
}
}

void rtio_sync(int channel)
{
rtio_chan_sel_write(channel);
while(rtio_o_level_read() != 0);
}

long long int rtio_get_counter(void)
{
rtio_counter_update_write(1);
return rtio_counter_read();
}

long long int rtio_get(int channel)
long long int rtio_get(int channel, long long int time_limit)
{
long long int r;

rtio_chan_sel_write(channel);
while(rtio_i_readable_read() || (rtio_o_level_read() != 0)) {
while(rtio_i_readable_read() || (rtio_get_counter() < time_limit)) {
if(rtio_i_overflow_read()) {
rtio_reset_logic_write(1);
rtio_reset_logic_write(0);
rtio_i_overflow_reset_write(1);
exception_raise(EID_RTIO_OVERFLOW);
}
if(rtio_i_readable_read()) {
@@ -93,7 +82,7 @@ int rtio_pileup_count(int channel)

void rtio_fud_sync(void)
{
rtio_sync(RTIO_FUD_CHANNEL);
while(rtio_get_counter() < previous_fud_end_time);
}

void rtio_fud(long long int fud_time)
@@ -113,8 +102,7 @@ void rtio_fud(long long int fud_time)
rtio_o_value_write(0);
rtio_o_we_write(1);
if(rtio_o_underflow_read()) {
rtio_reset_logic_write(1);
rtio_reset_logic_write(0);
rtio_o_underflow_reset_write(1);
exception_raise(EID_RTIO_UNDERFLOW);
}
}
3 changes: 1 addition & 2 deletions soc/runtime/rtio.h
Original file line number Diff line number Diff line change
@@ -5,9 +5,8 @@ void rtio_init(void);
void rtio_oe(int channel, int oe);
void rtio_set(long long int timestamp, int channel, int value);
void rtio_replace(long long int timestamp, int channel, int value);
void rtio_sync(int channel);
long long int rtio_get_counter(void);
long long int rtio_get(int channel);
long long int rtio_get(int channel, long long int time_limit);
int rtio_pileup_count(int channel);

void rtio_fud_sync(void);
1 change: 0 additions & 1 deletion soc/runtime/services.c
Original file line number Diff line number Diff line change
@@ -14,7 +14,6 @@ static const struct symbol syscalls[] = {
{"rtio_oe", rtio_oe},
{"rtio_set", rtio_set},
{"rtio_replace", rtio_replace},
{"rtio_sync", rtio_sync},
{"rtio_get_counter", rtio_get_counter},
{"rtio_get", rtio_get},
{"rtio_pileup_count", rtio_pileup_count},
5 changes: 3 additions & 2 deletions soc/targets/artiq.py
Original file line number Diff line number Diff line change
@@ -62,9 +62,10 @@ def __init__(self, platform, cpu_type="or1k", ramcon_type="minicon",
rtio_pads.append(fud)
self.submodules.rtiophy = rtio.phy.SimplePHY(
rtio_pads,
output_only_pads={rtio_pads[1], rtio_pads[2], rtio_pads[3]},
mini_pads={fud})
output_only_pads={rtio_pads[1], rtio_pads[2], rtio_pads[3], fud})
self.submodules.rtio = rtio.RTIO(self.rtiophy, self.clk_freq)
self.clock_domains.cd_rtio = ClockDomain()
self.comb += self.cd_rtio.clk.eq(ClockSignal())

if with_test_gen:
self.submodules.test_gen = _TestGen(platform.request("ttl", 4))

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