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  • 3 commits
  • 13 files changed
  • 1 contributor

Commits on Apr 1, 2013

  1. New bidirectional-capable Record API

    Sebastien Bourdeauducq committed Apr 1, 2013
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    6a3c413 View commit details
  2. bus: replace simple bus module with new bidirectional Record

    Sebastien Bourdeauducq committed Apr 1, 2013
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    29b4685 View commit details
  3. flow: adapt to new Record API

    Sebastien Bourdeauducq committed Apr 1, 2013
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    20bdd42 View commit details
24 changes: 24 additions & 0 deletions examples/basic/record.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,24 @@
from migen.fhdl.structure import *
from migen.fhdl.module import Module
from migen.fhdl import verilog
from migen.genlib.record import *

L = [
("position", [
("x", 10, DIR_M_TO_S),
("y", 10, DIR_M_TO_S),
]),
("color", 32, DIR_M_TO_S),
("stb", 1, DIR_M_TO_S),
("ack", 1, DIR_S_TO_M)
]

class Test(Module):
def __init__(self):
master = Record(L)
slave = Record(L)
self.comb += master.connect(slave)

print(verilog.convert(Test()))
print(layout_len(L))
print(layout_partial(L, "position/x", "color"))
20 changes: 0 additions & 20 deletions examples/basic/using_record.py

This file was deleted.

2 changes: 1 addition & 1 deletion migen/actorlib/spi.py
Original file line number Diff line number Diff line change
@@ -108,7 +108,7 @@ def get_fragment(self):
self._r_wc.dat_w.eq(self._r_wc.storage - 1),

wp.adr.eq(self._r_wa.storage),
wp.dat_w.eq(Cat(*self.token("sink").flatten())),
wp.dat_w.eq(self.token("sink").raw_bits()),

rp.adr.eq(self._r_ra.storage),
self._r_rd.status.eq(rp.dat_r)
6 changes: 3 additions & 3 deletions migen/actorlib/structuring.py
Original file line number Diff line number Diff line change
@@ -29,7 +29,7 @@ def get_process_fragment(self):
])

def pack_layout(l, n):
return [("chunk{0}".format(i), l) for i in range(n)]
return [("chunk"+str(i), l) for i in range(n)]

class Unpack(Actor):
def __init__(self, n, layout_to):
@@ -57,7 +57,7 @@ def get_fragment(self):
]
cases = {}
for i in range(self.n):
cases[i] = [Cat(*self.token("source").flatten()).eq(Cat(*self.token("sink").subrecord("chunk{0}".format(i)).flatten()))]
cases[i] = [self.token("source").raw_bits().eq(getattr(self.token("sink"), "chunk"+str(i)).raw_bits())]
comb.append(Case(mux, cases).makedefault())
return Fragment(comb, sync)

@@ -75,7 +75,7 @@ def get_fragment(self):
strobe_all = Signal()
cases = {}
for i in range(self.n):
cases[i] = [Cat(*self.token("source").subrecord("chunk{0}".format(i)).flatten()).eq(*self.token("sink").flatten())]
cases[i] = [getattr(self.token("source"), "chunk"+str(i)).raw_bits().eq(self.token("sink").raw_bits())]
comb = [
self.busy.eq(strobe_all),
self.endpoints["sink"].ack.eq(~strobe_all | self.endpoints["source"].ack),
103 changes: 49 additions & 54 deletions migen/bus/csr.py
Original file line number Diff line number Diff line change
@@ -1,23 +1,24 @@
from migen.fhdl.structure import *
from migen.fhdl.specials import Memory
from migen.fhdl.module import Module
from migen.bus.simple import *
from migen.bus.transactions import *
from migen.bank.description import CSRStorage
from migen.genlib.record import *
from migen.genlib.misc import chooser

data_width = 8

class Interface(SimpleInterface):
class Interface(Record):
def __init__(self):
SimpleInterface.__init__(self, Description(
(M_TO_S, "adr", 14),
(M_TO_S, "we", 1),
(M_TO_S, "dat_w", data_width),
(S_TO_M, "dat_r", data_width)))
Record.__init__(self, [
("adr", 14, DIR_M_TO_S),
("we", 1, DIR_M_TO_S),
("dat_w", data_width, DIR_M_TO_S),
("dat_r", data_width, DIR_S_TO_M)])

class Interconnect(SimpleInterconnect):
pass
class Interconnect(Module):
def __init__(self, master, slaves):
self.comb += master.connect(*slaves)

class Initiator(Module):
def __init__(self, generator, bus=None):
@@ -53,80 +54,74 @@ def _compute_page_bits(nwords):
else:
return 0

class SRAM:
class SRAM(Module):
def __init__(self, mem_or_size, address, read_only=None, bus=None):
if isinstance(mem_or_size, Memory):
self.mem = mem_or_size
mem = mem_or_size
else:
self.mem = Memory(data_width, mem_or_size//(data_width//8))
self.address = address
if self.mem.width > data_width:
self.csrw_per_memw = (self.mem.width + data_width - 1)//data_width
self.word_bits = bits_for(self.csrw_per_memw-1)
mem = Memory(data_width, mem_or_size//(data_width//8))
if mem.width > data_width:
csrw_per_memw = (self.mem.width + data_width - 1)//data_width
word_bits = bits_for(csrw_per_memw-1)
else:
self.csrw_per_memw = 1
self.word_bits = 0
page_bits = _compute_page_bits(self.mem.depth + self.word_bits)
csrw_per_memw = 1
word_bits = 0
page_bits = _compute_page_bits(mem.depth + word_bits)
if page_bits:
self._page = CSRStorage(page_bits, name=self.mem.name_override + "_page")
else:
self._page = None
if read_only is None:
if hasattr(self.mem, "bus_read_only"):
read_only = self.mem.bus_read_only
if hasattr(mem, "bus_read_only"):
read_only = mem.bus_read_only
else:
read_only = False
self.read_only = read_only
if bus is None:
bus = Interface()
self.bus = bus

def get_csrs(self):
if self._page is None:
return []
else:
return [self._page]

def get_fragment(self):
port = self.mem.get_port(write_capable=not self.read_only,
we_granularity=data_width if not self.read_only and self.word_bits else 0)
###

self.specials += mem
port = mem.get_port(write_capable=not read_only,
we_granularity=data_width if not read_only and word_bits else 0)

sel = Signal()
sel_r = Signal()
sync = [sel_r.eq(sel)]
comb = [sel.eq(self.bus.adr[9:] == self.address)]
self.sync += sel_r.eq(sel)
self.comb += sel.eq(self.bus.adr[9:] == address)

if self.word_bits:
word_index = Signal(self.word_bits)
word_expanded = Signal(self.csrw_per_memw*data_width)
sync.append(word_index.eq(self.bus.adr[:self.word_bits]))
comb += [
if word_bits:
word_index = Signal(word_bits)
word_expanded = Signal(csrw_per_memw*data_width)
sync.append(word_index.eq(self.bus.adr[:word_bits]))
self.comb += [
word_expanded.eq(port.dat_r),
If(sel_r,
chooser(word_expanded, word_index, self.bus.dat_r, n=self.csrw_per_memw, reverse=True)
chooser(word_expanded, word_index, self.bus.dat_r, n=csrw_per_memw, reverse=True)
)
]
if not self.read_only:
comb += [
If(sel & self.bus.we, port.we.eq((1 << self.word_bits) >> self.bus.adr[:self.word_bits])),
port.dat_w.eq(Replicate(self.bus.dat_w, self.csrw_per_memw))
if not read_only:
self.comb += [
If(sel & self.bus.we, port.we.eq((1 << word_bits) >> self.bus.adr[:self.word_bits])),
port.dat_w.eq(Replicate(self.bus.dat_w, csrw_per_memw))
]
else:
comb += [
If(sel_r,
self.bus.dat_r.eq(port.dat_r)
)
]
if not self.read_only:
comb += [
self.comb += If(sel_r, self.bus.dat_r.eq(port.dat_r))
if not read_only:
self.comb += [
port.we.eq(sel & self.bus.we),
port.dat_w.eq(self.bus.dat_w)
]

if self._page is None:
comb.append(port.adr.eq(self.bus.adr[self.word_bits:len(port.adr)]))
self.comb += port.adr.eq(self.bus.adr[word_bits:len(port.adr)])
else:
pv = self._page.storage
comb.append(port.adr.eq(Cat(self.bus.adr[self.word_bits:len(port.adr)-len(pv)], pv)))

return Fragment(comb, sync, specials={self.mem})
self.comb += port.adr.eq(Cat(self.bus.adr[word_bits:len(port.adr)-len(pv)], pv))

def get_csrs(self):
if self._page is None:
return []
else:
return [self._page]
62 changes: 27 additions & 35 deletions migen/bus/dfi.py
Original file line number Diff line number Diff line change
@@ -1,29 +1,31 @@
from migen.fhdl.structure import *
from migen.bus.simple import *
from migen.fhdl.module import Module
from migen.genlib.record import *

def phase_description(a, ba, d):
return Description(
(M_TO_S, "address", a),
(M_TO_S, "bank", ba),
(M_TO_S, "cas_n", 1),
(M_TO_S, "cke", 1),
(M_TO_S, "cs_n", 1),
(M_TO_S, "ras_n", 1),
(M_TO_S, "we_n", 1),
return [
("address", a, DIR_M_TO_S),
("bank", ba, DIR_M_TO_S),
("cas_n", 1, DIR_M_TO_S),
("cke", 1, DIR_M_TO_S),
("cs_n", 1, DIR_M_TO_S),
("ras_n", 1, DIR_M_TO_S),
("we_n", 1, DIR_M_TO_S),

(M_TO_S, "wrdata", d),
(M_TO_S, "wrdata_en", 1),
(M_TO_S, "wrdata_mask", d//8),
("wrdata", d, DIR_M_TO_S),
("wrdata_en", 1, DIR_M_TO_S),
("wrdata_mask", d//8, DIR_M_TO_S),

(M_TO_S, "rddata_en", 1),
(S_TO_M, "rddata", d),
(S_TO_M, "rddata_valid", 1)
)
("rddata_en", 1, DIR_M_TO_S),
("rddata", d, DIR_S_TO_M),
("rddata_valid", 1, DIR_S_TO_M)
]

class Interface:
class Interface(Record):
def __init__(self, a, ba, d, nphases=1):
self.pdesc = phase_description(a, ba, d)
self.phases = [SimpleInterface(self.pdesc) for i in range(nphases)]
layout = [("p"+str(i), phase_description(a, ba, d)) for i in range(nphases)]
Record.__init__(self, layout)
self.phases = [getattr(self, "p"+str(i)) for i in range(nphases)]
for p in self.phases:
p.cas_n.reset = 1
p.cs_n.reset = 1
@@ -35,28 +37,18 @@ def get_standard_names(self, m2s=True, s2m=True):
r = []
add_suffix = len(self.phases) > 1
for n, phase in enumerate(self.phases):
for signal in self.pdesc.desc:
if (m2s and signal[0] == M_TO_S) or (s2m and signal[0] == S_TO_M):
for field, size, direction in phase.layout:
if (m2s and direction == DIR_M_TO_S) or (s2m and direction == DIR_S_TO_M):
if add_suffix:
if signal[0] == M_TO_S:
if direction == DIR_M_TO_S:
suffix = "_p" + str(n)
else:
suffix = "_w" + str(n)
else:
suffix = ""
r.append(("dfi_" + signal[1] + suffix, getattr(phase, signal[1])))
r.append(("dfi_" + field + suffix, getattr(phase, field)))
return r

def interconnect_stmts(master, slave):
r = []
for pm, ps in zip(master.phases, slave.phases):
r += simple_interconnect_stmts(master.pdesc, pm, [ps])
return r

class Interconnect:
class Interconnect(Module):
def __init__(self, master, slave):
self.master = master
self.slave = slave

def get_fragment(self):
return Fragment(interconnect_stmts(self.master, self.slave))
self.comb += master.connect(slave)
47 changes: 0 additions & 47 deletions migen/bus/simple.py

This file was deleted.

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