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Commit 8e4b898

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enjoy-digitalsbourdeauducq
authored andcommittedOct 20, 2014
use new direct access on endpoints
1 parent 34ed315 commit 8e4b898

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3 files changed

+11
-11
lines changed

3 files changed

+11
-11
lines changed
 

‎misoclib/framebuffer/format.py

+5-5
Original file line numberDiff line numberDiff line change
@@ -91,7 +91,7 @@ def __init__(self, pack_factor):
9191
If(active,
9292
[getattr(getattr(self.phy.payload, p), c).eq(getattr(getattr(self.pixels.payload, p), c)[skip:])
9393
for p in ["p"+str(i) for i in range(pack_factor)] for c in ["r", "g", "b"]],
94-
self.phy.payload.de.eq(1)
94+
self.phy.de.eq(1)
9595
),
9696
self.pixels.ack.eq(self.phy.ack & active)
9797
]
@@ -109,8 +109,8 @@ def __init__(self, pack_factor):
109109

110110
If(hcounter == 0, hactive.eq(1)),
111111
If(hcounter == tr.hres, hactive.eq(0)),
112-
If(hcounter == tr.hsync_start, self.phy.payload.hsync.eq(1)),
113-
If(hcounter == tr.hsync_end, self.phy.payload.hsync.eq(0)),
112+
If(hcounter == tr.hsync_start, self.phy.hsync.eq(1)),
113+
If(hcounter == tr.hsync_end, self.phy.hsync.eq(0)),
114114
If(hcounter == tr.hscan,
115115
hcounter.eq(0),
116116
If(vcounter == tr.vscan,
@@ -123,8 +123,8 @@ def __init__(self, pack_factor):
123123

124124
If(vcounter == 0, vactive.eq(1)),
125125
If(vcounter == tr.vres, vactive.eq(0)),
126-
If(vcounter == tr.vsync_start, self.phy.payload.vsync.eq(1)),
127-
If(vcounter == tr.vsync_end, self.phy.payload.vsync.eq(0))
126+
If(vcounter == tr.vsync_start, self.phy.vsync.eq(1)),
127+
If(vcounter == tr.vsync_end, self.phy.vsync.eq(0))
128128
)
129129
]
130130

‎misoclib/memtest/__init__.py

+2-2
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,7 @@ def __init__(self, lasmim):
5757
self._dma.trigger.eq(self._r_shoot.re),
5858
self._dma.data.stb.eq(en),
5959
lfsr.ce.eq(en & self._dma.data.ack),
60-
self._dma.data.payload.d.eq(lfsr.o)
60+
self._dma.data.d.eq(lfsr.o)
6161
]
6262

6363
def get_csrs(self):
@@ -87,7 +87,7 @@ def __init__(self, lasmim):
8787
If(self._r_reset.re,
8888
err_cnt.eq(0)
8989
).Elif(self._dma.data.stb,
90-
If(self._dma.data.payload.d != lfsr.o, err_cnt.eq(err_cnt + 1))
90+
If(self._dma.data.d != lfsr.o, err_cnt.eq(err_cnt + 1))
9191
)
9292
]
9393

‎misoclib/uart/__init__.py

+4-4
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ def __init__(self, pads, tuning_word):
2121
rx_bitcount = Signal(4)
2222
rx_busy = Signal()
2323
rx_done = self.source.stb
24-
rx_data = self.source.payload.d
24+
rx_data = self.source.d
2525
self.sync += [
2626
rx_done.eq(0),
2727
rx_r.eq(rx),
@@ -73,7 +73,7 @@ def __init__(self, pads, tuning_word):
7373
self.sync += [
7474
self.sink.ack.eq(0),
7575
If(self.sink.stb & ~tx_busy & ~self.sink.ack,
76-
tx_reg.eq(self.sink.payload.d),
76+
tx_reg.eq(self.sink.d),
7777
tx_bitcount.eq(0),
7878
tx_busy.eq(1),
7979
pads.tx.eq(0)
@@ -120,12 +120,12 @@ def __init__(self, pads, clk_freq, baud=115200):
120120
self.sync += [
121121
If(self._r_rxtx.re,
122122
self.tx.sink.stb.eq(1),
123-
self.tx.sink.payload.d.eq(self._r_rxtx.r),
123+
self.tx.sink.d.eq(self._r_rxtx.r),
124124
).Elif(self.tx.sink.ack,
125125
self.tx.sink.stb.eq(0)
126126
),
127127
If(self.rx.source.stb,
128-
self._r_rxtx.w.eq(self.rx.source.payload.d)
128+
self._r_rxtx.w.eq(self.rx.source.d)
129129
)
130130
]
131131
self.comb += [

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