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  • 2 commits
  • 6 files changed
  • 2 contributors

Commits on Nov 14, 2012

  1. lm32: split lm32_include.v

    Sebastien Bourdeauducq committed Nov 14, 2012
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    d15d982 View commit details
  2. lm32: replace $clog2 with macro

    Unfortunately, XST does not support $clog2 with the localparam keyword
    (the parameter keyword works just fine). Define a macro which replaces the
    call with a constant function.
    
    This commit can be reverted if the bug in XST is fixed.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
    mwalle authored and Sebastien Bourdeauducq committed Nov 14, 2012
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    a0ff666 View commit details
Showing with 75 additions and 57 deletions.
  1. +50 −0 verilog/lm32/lm32_config.v
  2. +3 −3 verilog/lm32/lm32_dcache.v
  3. +3 −3 verilog/lm32/lm32_icache.v
  4. +1 −33 verilog/lm32/lm32_include.v
  5. +9 −9 verilog/lm32/lm32_instruction_unit.v
  6. +9 −9 verilog/lm32/lm32_load_store_unit.v
50 changes: 50 additions & 0 deletions verilog/lm32/lm32_config.v
Original file line number Diff line number Diff line change
@@ -0,0 +1,50 @@
`ifdef LM32_CONFIG_V
`else
`define LM32_CONFIG_V

`define CFG_EBA_RESET 32'h00860000
`define CFG_DEBA_RESET 32'h10000000

`define CFG_PL_MULTIPLY_ENABLED
`define CFG_PL_BARREL_SHIFT_ENABLED
`define CFG_SIGN_EXTEND_ENABLED
`define CFG_MC_DIVIDE_ENABLED
`define CFG_EBR_POSEDGE_REGISTER_FILE

`define CFG_ICACHE_ENABLED
`define CFG_ICACHE_ASSOCIATIVITY 1
`define CFG_ICACHE_SETS 256
`define CFG_ICACHE_BYTES_PER_LINE 16
`define CFG_ICACHE_BASE_ADDRESS 32'h0
`define CFG_ICACHE_LIMIT 32'h7fffffff

`define CFG_DCACHE_ENABLED
`define CFG_DCACHE_ASSOCIATIVITY 1
`define CFG_DCACHE_SETS 256
`define CFG_DCACHE_BYTES_PER_LINE 16
`define CFG_DCACHE_BASE_ADDRESS 32'h0
`define CFG_DCACHE_LIMIT 32'h7fffffff

// Enable Debugging
//`define CFG_JTAG_ENABLED
//`define CFG_JTAG_UART_ENABLED
//`define CFG_DEBUG_ENABLED
//`define CFG_HW_DEBUG_ENABLED
//`define CFG_ROM_DEBUG_ENABLED
//`define CFG_BREAKPOINTS 32'h4
//`define CFG_WATCHPOINTS 32'h4
//`define CFG_EXTERNAL_BREAK_ENABLED
//`define CFG_GDBSTUB_ENABLED

function integer clog2;
input integer value;
begin
value = value - 1;
for (clog2 = 0; value > 0; clog2 = clog2 + 1)
value = value >> 1;
end
endfunction

`define CLOG2 clog2

`endif
6 changes: 3 additions & 3 deletions verilog/lm32/lm32_dcache.v
Original file line number Diff line number Diff line change
@@ -112,14 +112,14 @@ parameter bytes_per_line = 16; // Number of bytes per c
parameter base_address = 0; // Base address of cachable memory
parameter limit = 0; // Limit (highest address) of cachable memory

localparam addr_offset_width = $clog2(bytes_per_line)-2;
localparam addr_set_width = $clog2(sets);
localparam addr_offset_width = `CLOG2(bytes_per_line)-2;
localparam addr_set_width = `CLOG2(sets);
localparam addr_offset_lsb = 2;
localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
localparam addr_set_lsb = (addr_offset_msb+1);
localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
localparam addr_tag_lsb = (addr_set_msb+1);
localparam addr_tag_msb = $clog2(`CFG_DCACHE_LIMIT-`CFG_DCACHE_BASE_ADDRESS);
localparam addr_tag_msb = `CLOG2(`CFG_DCACHE_LIMIT-`CFG_DCACHE_BASE_ADDRESS);
localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);

/////////////////////////////////////////////////////
6 changes: 3 additions & 3 deletions verilog/lm32/lm32_icache.v
Original file line number Diff line number Diff line change
@@ -119,14 +119,14 @@ parameter bytes_per_line = 16; // Number of bytes per c
parameter base_address = 0; // Base address of cachable memory
parameter limit = 0; // Limit (highest address) of cachable memory

localparam addr_offset_width = $clog2(bytes_per_line)-2;
localparam addr_set_width = $clog2(sets);
localparam addr_offset_width = `CLOG2(bytes_per_line)-2;
localparam addr_set_width = `CLOG2(sets);
localparam addr_offset_lsb = 2;
localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
localparam addr_set_lsb = (addr_offset_msb+1);
localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
localparam addr_tag_lsb = (addr_set_msb+1);
localparam addr_tag_msb = $clog2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS);
localparam addr_tag_msb = `CLOG2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS);
localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);

/////////////////////////////////////////////////////
34 changes: 1 addition & 33 deletions verilog/lm32/lm32_include.v
Original file line number Diff line number Diff line change
@@ -58,39 +58,7 @@
// Common configuration options
//

`define CFG_EBA_RESET 32'h00860000
`define CFG_DEBA_RESET 32'h10000000

`define CFG_PL_MULTIPLY_ENABLED
`define CFG_PL_BARREL_SHIFT_ENABLED
`define CFG_SIGN_EXTEND_ENABLED
`define CFG_MC_DIVIDE_ENABLED
`define CFG_EBR_POSEDGE_REGISTER_FILE

`define CFG_ICACHE_ENABLED
`define CFG_ICACHE_ASSOCIATIVITY 1
`define CFG_ICACHE_SETS 256
`define CFG_ICACHE_BYTES_PER_LINE 16
`define CFG_ICACHE_BASE_ADDRESS 32'h0
`define CFG_ICACHE_LIMIT 32'h7fffffff

`define CFG_DCACHE_ENABLED
`define CFG_DCACHE_ASSOCIATIVITY 1
`define CFG_DCACHE_SETS 256
`define CFG_DCACHE_BYTES_PER_LINE 16
`define CFG_DCACHE_BASE_ADDRESS 32'h0
`define CFG_DCACHE_LIMIT 32'h7fffffff

// Enable Debugging
//`define CFG_JTAG_ENABLED
//`define CFG_JTAG_UART_ENABLED
//`define CFG_DEBUG_ENABLED
//`define CFG_HW_DEBUG_ENABLED
//`define CFG_ROM_DEBUG_ENABLED
//`define CFG_BREAKPOINTS 32'h4
//`define CFG_WATCHPOINTS 32'h4
//`define CFG_EXTERNAL_BREAK_ENABLED
//`define CFG_GDBSTUB_ENABLED
`include "lm32_config.v"

//
// End of common configuration options
18 changes: 9 additions & 9 deletions verilog/lm32/lm32_instruction_unit.v
Original file line number Diff line number Diff line change
@@ -179,7 +179,7 @@ parameter base_address = 0; // Base address of cacha
parameter limit = 0; // Limit (highest address) of cachable memory

// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used
localparam addr_offset_width = bytes_per_line == 4 ? 1 : $clog2(bytes_per_line)-2;
localparam addr_offset_width = bytes_per_line == 4 ? 1 : `CLOG2(bytes_per_line)-2;
localparam addr_offset_lsb = 2;
localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);

@@ -388,18 +388,18 @@ reg alternate_eba_taken;
// ----- Parameters -------
.pmi_family (`LATTICE_FAMILY),

//.pmi_addr_depth_a (1 << $clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
//.pmi_addr_width_a ($clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
//.pmi_addr_depth_a (1 << `CLOG2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
//.pmi_addr_width_a (`CLOG2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
//.pmi_data_width_a (`LM32_WORD_WIDTH),
//.pmi_addr_depth_b (1 << $clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
//.pmi_addr_width_b ($clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
//.pmi_addr_depth_b (1 << `CLOG2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
//.pmi_addr_width_b (`CLOG2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
//.pmi_data_width_b (`LM32_WORD_WIDTH),

.pmi_addr_depth_a (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1),
.pmi_addr_width_a ($clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
.pmi_addr_width_a (`CLOG2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
.pmi_data_width_a (`LM32_WORD_WIDTH),
.pmi_addr_depth_b (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1),
.pmi_addr_width_b ($clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
.pmi_addr_width_b (`CLOG2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
.pmi_data_width_b (`LM32_WORD_WIDTH),

.pmi_regmode_a ("noreg"),
@@ -418,8 +418,8 @@ reg alternate_eba_taken;
.ResetB (rst_i),
.DataInA ({32{1'b0}}),
.DataInB (irom_store_data_m),
.AddressA (pc_a[$clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]),
.AddressB (irom_address_xm[$clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]),
.AddressA (pc_a[`CLOG2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]),
.AddressB (irom_address_xm[`CLOG2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]),
.ClockEnA (!stall_a),
.ClockEnB (!stall_x || !stall_m),
.WrA (`FALSE),
18 changes: 9 additions & 9 deletions verilog/lm32/lm32_load_store_unit.v
Original file line number Diff line number Diff line change
@@ -139,7 +139,7 @@ parameter base_address = 0; // Base address of cacha
parameter limit = 0; // Limit (highest address) of cachable memory

// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used
localparam addr_offset_width = bytes_per_line == 4 ? 1 : $clog2(bytes_per_line)-2;
localparam addr_offset_width = bytes_per_line == 4 ? 1 : `CLOG2(bytes_per_line)-2;
localparam addr_offset_lsb = 2;
localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);

@@ -293,18 +293,18 @@ reg wb_load_complete; // Indicates when a Wish
// ----- Parameters -------
.pmi_family (`LATTICE_FAMILY),

//.pmi_addr_depth_a (1 << $clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
//.pmi_addr_width_a ($clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
//.pmi_addr_depth_a (1 << `CLOG2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
//.pmi_addr_width_a (`CLOG2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
//.pmi_data_width_a (`LM32_WORD_WIDTH),
//.pmi_addr_depth_b (1 << $clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
//.pmi_addr_width_b ($clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
//.pmi_addr_depth_b (1 << `CLOG2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
//.pmi_addr_width_b (`CLOG2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
//.pmi_data_width_b (`LM32_WORD_WIDTH),

.pmi_addr_depth_a (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1),
.pmi_addr_width_a ($clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
.pmi_addr_width_a (`CLOG2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
.pmi_data_width_a (`LM32_WORD_WIDTH),
.pmi_addr_depth_b (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1),
.pmi_addr_width_b ($clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
.pmi_addr_width_b (`CLOG2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
.pmi_data_width_b (`LM32_WORD_WIDTH),

.pmi_regmode_a ("noreg"),
@@ -323,8 +323,8 @@ reg wb_load_complete; // Indicates when a Wish
.ResetB (rst_i),
.DataInA ({32{1'b0}}),
.DataInB (dram_store_data_m),
.AddressA (load_store_address_x[$clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)+2-1:2]),
.AddressB (load_store_address_m[$clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)+2-1:2]),
.AddressA (load_store_address_x[`CLOG2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)+2-1:2]),
.AddressB (load_store_address_m[`CLOG2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)+2-1:2]),
// .ClockEnA (!stall_x & (load_x | store_x)),
.ClockEnA (!stall_x),
.ClockEnB (!stall_m),