dvisampler: use hard differential phase detector

m-labs · Sep 14, 2013 · ffe4bff · ffe4bff
1 parent 8bc1620
commit ffe4bff
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Showing 5 changed files with 157 additions and 177 deletions.
diff --git a/milkymist/dvisampler/__init__.py b/milkymist/dvisampler/__init__.py
@@ -18,27 +18,10 @@ def __init__(self, pads, asmiport, n_dma_slots=2):
 
 		for datan in range(3):
 			name = "data" + str(datan)
-			invert = False
-			if hasattr(pads, name + "_p"):
-				s = Signal()
-				self.specials += Instance("IBUFDS",
-					Instance.Input("I", getattr(pads, name + "_p")),
-					Instance.Input("IB", getattr(pads, name + "_n")),
-					Instance.Output("O", s)		
-				)
-			else:
-				try:
-					s = getattr(pads, name)
-				except AttributeError:
-					s = getattr(pads, name + "_n")
-					invert = True
 
-			cap = DataCapture(8, invert)
+			cap = DataCapture(getattr(pads, name + "_p"), getattr(pads, name + "_n"), 8)
 			setattr(self.submodules, name + "_cap", cap)
-			self.comb += [
-				cap.pad.eq(s),
-				cap.serdesstrobe.eq(self.clocking.serdesstrobe)
-			]
+			self.comb += cap.serdesstrobe.eq(self.clocking.serdesstrobe)
 
 			charsync = CharSync()
 			setattr(self.submodules, name + "_charsync", charsync)
@@ -64,8 +47,6 @@ def __init__(self, pads, asmiport, n_dma_slots=2):
 			self.chansync.data_in2.eq(self.data2_decod.output),
 		]
 
-		###
-
 		self.submodules.syncpol = SyncPolarity()
 		self.comb += [
 			self.syncpol.valid_i.eq(self.chansync.chan_synced),

diff --git a/milkymist/dvisampler/clocking.py b/milkymist/dvisampler/clocking.py
@@ -12,77 +12,46 @@ def __init__(self, pads):
 		self.clock_domains._cd_pix = ClockDomain()
 		self.clock_domains._cd_pix5x = ClockDomain()
 		self.clock_domains._cd_pix10x = ClockDomain(reset_less=True)
-		self.clock_domains._cd_pix20x = ClockDomain(reset_less=True)
 
 		###
 
-		if hasattr(pads, "clk_p"):
-			clkin = Signal()
-			self.specials += Instance("IBUFDS",
-				Instance.Input("I", pads.clk_p),
-				Instance.Input("IB", pads.clk_n),
-				Instance.Output("O", clkin)		
-			)
-		else:
-			clkin = pads.clk
+		clk_se = Signal()
+		self.specials += Instance("IBUFDS", i_I=pads.clk_p, i_IB=pads.clk_n, o_O=clk_se)
 
 		clkfbout = Signal()
 		pll_locked = Signal()
 		pll_clk0 = Signal()
 		pll_clk1 = Signal()
 		pll_clk2 = Signal()
-		pll_clk3 = Signal()
 		self.specials += Instance("PLL_BASE",
-			Instance.Parameter("CLKIN_PERIOD", 26.7),
-			Instance.Parameter("CLKFBOUT_MULT", 20),
-			Instance.Parameter("CLKOUT0_DIVIDE", 1),  # pix20x
-			Instance.Parameter("CLKOUT1_DIVIDE", 4),  # pix5x
-			Instance.Parameter("CLKOUT2_DIVIDE", 20), # pix
-			Instance.Parameter("CLKOUT3_DIVIDE", 2),  # pix10x
-			Instance.Parameter("COMPENSATION", "INTERNAL"),
-
-			Instance.Output("CLKFBOUT", clkfbout),
-			# WARNING: Do not touch the order of those clocks, or PAR fails.
-			Instance.Output("CLKOUT0", pll_clk0),
-			Instance.Output("CLKOUT1", pll_clk1),
-			Instance.Output("CLKOUT2", pll_clk2),
-			Instance.Output("CLKOUT3", pll_clk3),
-			Instance.Output("LOCKED", pll_locked),
-			Instance.Input("CLKFBIN", clkfbout),
-			Instance.Input("CLKIN", clkin),
-			Instance.Input("RST", self._r_pll_reset.storage)
-		)
+			p_CLKIN_PERIOD=26.7,
+			p_CLKFBOUT_MULT=20,
+			p_CLKOUT0_DIVIDE=2,  # pix10x
+			p_CLKOUT1_DIVIDE=4,  # pix5x
+			p_CLKOUT2_DIVIDE=20, # pix
+			p_COMPENSATION="INTERNAL",
+
+			i_CLKIN=clk_se,
+			o_CLKOUT0=pll_clk0, o_CLKOUT1=pll_clk1, o_CLKOUT2=pll_clk2,
+			o_CLKFBOUT=clkfbout, i_CLKFBIN=clkfbout,
+			o_LOCKED=pll_locked, i_RST=self._r_pll_reset.storage)
 
 		locked_async = Signal()
-		self.specials += Instance("BUFPLL",
-			Instance.Parameter("DIVIDE", 4),
-			Instance.Input("PLLIN", pll_clk0),
-			Instance.Input("GCLK", ClockSignal("pix5x")),
-			Instance.Input("LOCKED", pll_locked),
-			Instance.Output("IOCLK", self._cd_pix20x.clk),
-			Instance.Output("LOCK", locked_async),
-			Instance.Output("SERDESSTROBE", self.serdesstrobe)
-		)
-		self.specials += Instance("BUFG",
-			Instance.Input("I", pll_clk1), Instance.Output("O", self._cd_pix5x.clk))
-		self.specials += Instance("BUFG",
-			Instance.Input("I", pll_clk2), Instance.Output("O", self._cd_pix.clk))
-		self.specials += Instance("BUFG",
-			Instance.Input("I", pll_clk3), Instance.Output("O", self._cd_pix10x.clk))
-		self.specials += MultiReg(locked_async, self.locked, "sys")
+		self.specials += [
+			Instance("BUFPLL", p_DIVIDE=2,
+				i_PLLIN=pll_clk0, i_GCLK=ClockSignal("pix5x"), i_LOCKED=pll_locked,
+				o_IOCLK=self._cd_pix10x.clk, o_LOCK=locked_async, o_SERDESSTROBE=self.serdesstrobe),
+			Instance("BUFG", i_I=pll_clk1, o_O=self._cd_pix5x.clk),
+			Instance("BUFG", i_I=pll_clk2, o_O=self._cd_pix.clk),
+			MultiReg(locked_async, self.locked, "sys")
+		]
 		self.comb += self._r_locked.status.eq(self.locked)
 
 		# sychronize pix+pix5x reset
 		pix_rst_n = 1
 		for i in range(2):
 			new_pix_rst_n = Signal()
-			self.specials += Instance("FDCE",
-				Instance.Input("D", pix_rst_n),
-				Instance.Input("CE", 1),
-				Instance.Input("C", ClockSignal("pix")),
-				Instance.Input("CLR", ~locked_async),
-				Instance.Output("Q", new_pix_rst_n)
-			)
+			self.specials += Instance("FDCE", i_D=pix_rst_n, i_CE=1, i_C=ClockSignal("pix"),
+				i_CLR=~locked_async, o_Q=new_pix_rst_n)
 			pix_rst_n = new_pix_rst_n
-		self.comb += self._cd_pix.rst.eq(~pix_rst_n)
-		self.comb += self._cd_pix5x.rst.eq(~pix_rst_n)
+		self.comb += self._cd_pix.rst.eq(~pix_rst_n), self._cd_pix5x.rst.eq(~pix_rst_n)